MAX8785AETI+T Maxim Integrated Products, MAX8785AETI+T Datasheet - Page 8

• Manufacturer Part Number: MAX8785AETI+T
• Description: IC CCFL CTRL 28-TQFN
• Manufacturer: Maxim Integrated Products
• Type: CCFL Controllerr

Specifications of MAX8785AETI+T

• Current - Supply: 1.5mA
• Voltage - Supply: 4.5 V ~ 28 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output: -
• Frequency: -
• Lead Free Status / Rohs Status: Details

Full-Bridge Controller for
Piezoelectric Transformers
8
8
PIN
10
11
12
13
14
15
16
17
18
19
20
21
22
23
_______________________________________________________________________________________
_______________________________________________________________________________________
1
2
3
4
5
6
7
8
9
PCOMP
LSYNC
NAME
COMP
PGND
RATE
CNTL
BST2
BST1
TFLT
V
V
GH2
GH1
VFB
GL2
GL1
FLT
LX2
LX1
IFB
HF
LF
DD2
DD1
Duty Ratio Ramp Adjustment Input. Connect a feed-forward network between BATT and RATE to adjust the
slope of the internal ramp that adjusts the H-bridge duty cycle with input voltage.
Shutdown Control Input. The IC shuts down when
Brightness Control Input. The usable brightness control range is from 0 to 2V. V
minimum brightness (10% DPWM duty cycle), V
cycle). For details, see the Dimming Control section.
DPWM Sync Input. DPWM frequency can be synchronized with an external signal on LSYNC. When SEL is
connected to V
Dimming Control section.
Fault Status Output. FLT is an open-drain output and requires a pullup resistor between V
normal conditions, the FLT output is high impedance. FLT pulls low when a fault condition occurs; FLT is
reset on either power or
Fault Time-Out Setting. Connect a capacitor from TFLT to GND to set the time out period. For details, see
the Setting the Fault Delay Time section.
Maximum Switching Frequency Adjustment Input. Connect a resistor from HF to GND to set the maximum
sweeping frequency of the main oscillator.
DPWM Frequency Adjustment Input. Connect a resistor from LF to GND to set the DPWM oscillator
Phase-Lock Loop (PLL) Compensation Pin. Connect a capacitor between PCOMP and GND to compensate
the PLL.
Transconductance Error-Amplifier Output. The COMP voltage controls the voltage-controlled oscillator to
adjust the switching frequency. Connect a capacitor from COMP to GND.
Lamp Current-Feedback Input. IFB regulates the average lamp-current feedback to 800mV (typ) by
controlling the switching frequency. For details, see the Lamp-Current Regulation section.
Secondary Voltage-Feedback Input. A resistive voltage-divider between the high-voltage terminal of the
transformer and GND sets the maximum peak lamp voltage during striking and lamp-out fault. Add 1nF
capacitor from VFB to GND for noise rejection. For details, see the Lamp-Out Detection and Overvoltage
Protection section.
GH2 Gate-Driver Return. LX2 is the input to the primary current-limit comparator. The controller senses the
voltage across the low-side MOSFET (LX2 - PGND) for primary overcurrent condition.
High-Side MOSFET Gate-Driver Output
GH2 Gate-Driver Supply Input. Connect a 0.1μF capacitor from LX2 to BST2.
GL2 Low-Side Gate-Driver Supply Input. Connect V
Low-Side MOSFET Gate-Driver Output
Power Ground. PGND is the return of GL1 and GL2 gate drivers.
Low-Side MOSFET Gate-Driver Output
GL1 Low-Side Gate-Driver Supply Input. Connect V
GH1 Gate-Driver Supply Input. Connect a 0.1μF capacitor from LX1 to BST1.
High-Side MOSFET Gate-Driver Output
GH1 Gate-Driver Return. LX1 is the input to the primary current-limit comparator. The controller senses the
voltage across the low-side MOSFET (LX1 - PGND) for primary overcurrent condition.
CC
, the duty cycle of the LSYNC signal determines the brightness. For details, see the
cycle.
DD1
CNTL
FUNCTION
DD2
to V
= 2V represents the full brightness (100% DPWM duty
to V
CC
is pulled to GND.
. Bypass V
CC
. Bypass V
DD1
with a 1μF capacitor to PGND.
DD2
with a 1μF capacitor to PGND.
CNTL
Pin Description
= 0 represents the
CC
and FLT. Under