IR3510MTRPBF International Rectifier, IR3510MTRPBF Datasheet - Page 15

• Manufacturer Part Number: IR3510MTRPBF
• Description: IC XPHASE CONTROL 32-MLPQ
• Manufacturer: International Rectifier
• Series: XPhase™r

Specifications of IR3510MTRPBF

• Applications: Processor
• Mounting Type: Surface Mount
• Package / Case: 32-MLPQ
• Package: 32-Lead MLPQ
• Circuit: X-Phase Control IC
• Pbf: PbF Option Available
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Voltage - Supply: -
• Operating Temperature: -
• Other names: IR3510MTRPBFTR

PHASE IC
CLOCK
PULSE
PWMRMP
GATEH
GATEL
PWM Operation
The PWM comparator is located in the Phase IC. Upon receiving a clock pulse, the PWM latch is set, the
PWMRMP voltage begins to increase, the low side driver is turned off, and the high side driver is then turned on.
When the PWMRMP voltage exceeds the EAOUT voltage the PWM latch is reset. This turns off the high side
driver, turns on the low side driver, and activates the Ramp Discharge Clamp. The clamp quickly discharges the
PWMRMP capacitor to the VDAC voltage of the Control IC until the next clock pulse.
The PWM latch is reset dominant allowing all phases to go to zero duty cycle within a few tens of nanoseconds in
response to a load step decrease. Phases can overlap and go to 100% duty cycle in response to a load step
increase with turn-on gated by the clock pulses. An Error Amp output voltage greater than the common mode input
range of the PWM comparator results in 100% duty cycle regardless of the voltage of the PWM ramp. This
arrangement guarantees the Error Amp is always in control and can demand 0 to 100% duty cycle as required. It
also favors response to a load step decrease which is appropriate given the low output to input voltage ratio of
most systems. The inductor current will increase much more rapidly than decrease in response to load transients.
This control method is designed to provide “single cycle transient response” where the inductor current changes in
response to load transients within a single switching cycle maximizing the effectiveness of the power train and
minimizing the output capacitor requirements. An additional advantage is that differences in ground or input
voltage at the phases have no effect on operation since the PWM ramps are referenced to VREF.
Body Braking
In a conventional synchronous buck converter, the minimum time required to reduce the current in the inductor in
response to a load step decrease is;
The slew rate of the inductor current can be significantly increased by turning off the synchronous rectifier in
response to a load step decrease. The switch node voltage is then forced to decrease until conduction of the
synchronous rectifier’s body diode occurs. This increases the voltage across the inductor from Vout to Vout +
V
decrease is now;
Since the voltage drop in the body diode is often higher than output voltage, the inductor current slew rate can be
increased by 2X or more. This patent pending technique is referred to as “body braking” and is accomplished
through the “0% Duty Cycle Comparator” located in the Phase IC. If the Error Amp’s output voltage drops below
91% of the VDAC voltage this comparator turns off the low side gate driver.
BODY DIODE
EAIN
VDAC
Page 15 of 36
. The minimum time required to reduce the current in the inductor in response to a load transient
TM
STEADY-STATE
OPERATION
DUTY CYCLE INCREASE
DUE TO LOAD
INCREASE
T
SLEW
Figure 3 – PWM Operating Waveforms
= [L x (I
T
SLEW
IR Confidential
= [L x (I
MAX
− I
DUTY CYCLE DECREASE
DUE TO VIN INCREASE
(FEED-FORWARD)
MIN
MAX
)] / (Vout + V
− I
MIN
Body-Braking
Threshold
)] / Vout
BODY DIODE
DUTY CYCLE DECREASE DUE TO LOAD
DECREASE (BODY BRAKING) OR FAULT
(VCC UV, VCCVID UV, OCP, VID=11111X)
)
May 18, 2009
IR3510
STEADY-STATE
OPERATION