MAX8588ETM+ Maxim Integrated Products, MAX8588ETM+ Datasheet - Page 21

• Manufacturer Part Number: MAX8588ETM+
• Description: IC PMIC HI EFF LOW IQ 48-TQFN
• Manufacturer: Maxim Integrated Products
• Type: Low-IQ PMICr

Specifications of MAX8588ETM+

• Applications: Processor
• Voltage - Supply: 2.6 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFN Exposed Pad
• Output Voltage Range: 1.2375 V to 1.2625 V
• Input Voltage Range: 2.4 V to 5.5 V
• Input Current: 32 uA
• Power Dissipation: 2105 mW
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Input Voltage: 5.5V
• No. Of Outputs: 1
• Power Dissipation Pd: 2.105W
• Supply Voltage Range: 2.6V To 5.5V
• No. Of Pins: 48
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Frequency: 1MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Alternately, LBI and DBI can be set with separate two-
resistor-dividers. Choose the lower resistor of the divider
chain to be 250kΩ or less (R5 and R7 in Figure 4). The
equations for upper divider-resistors as a function of
each threshold are then:
When resistors are used to set V
is 1.00V. When resistors are used to set V
threshold at DBI is 1.232V. A resistor-set threshold can
also be used for only one of DBI or LBI. The other
threshold can then be factory set by connecting the
appropriate input to IN.
If BKBT is not powered, DBO does not function and is
high impedance. DBO is expected to connect to
nBATT_FAULT on Intel CPUs. If BKBT is not powered,
LBO does not function and is high impedance.
POK is an open-drain output that goes low when any
activated regulator (V1–V6) is below its regulation
threshold. POK does not monitor V7. When all active
output voltages are within 10% of regulation, POK is
high impedance. POK does not flag an out-of-regula-
tion condition while V3 is transitioning between voltages
set by serial programming or when any regulator chan-
nel has been turned off. POK momentarily goes low
when any regulator is turned on, but returns high when
that regulator reaches regulation. When all regulators
(V1–V6) are off, POK is forced low. If the input voltage
is below the UVLO threshold, POK is held low and
maintains a valid low output with IN as low as 1V. If
BKBT is not powered, POK does not function and is
high impedance.
Figure 4. Setting the Low-Battery and Dead-Battery Thresholds
with Separate Resistor-Dividers. The values shown set a DBI
threshold of 3.3V and an LBI threshold of 3.5V (no resistors are
needed for factory-preset thresholds).
MAIN BATTERY
334kΩ
200kΩ
R4 = R5 (V
Dynamic Core for PDAs and Smartphones
R4
R5
______________________________________________________________________________________
R6 = R7 (V
500kΩ
200kΩ
R6
R7
DB
/ 1.232) - 1)
Power-OK Output (POK)
LB
IN
DBI (1.232V THRESHOLD)
LBI (1.00V THRESHOLD)
LB
- 1)
High-Efficiency, Low-I
, the threshold at LBI
MAX8588
DB
, the
Typical processor connections have only power-control
pins, typically labeled PWR_EN and SYS_EN. The
MAX8588 provides numerous on/off control pins for
maximum flexibility. In a typical application, many of
these pins are connected together. ON1, ON2, and
ON6 typically connect to SYS_EN. ON3, ON4, and ON5
typically connect to PWR_EN. V7 remains on as long as
the main or backup power is connected. Sequencing is
not performed internally on the MAX8588; however, all
ON_ inputs have hysteresis and can connect to RC net-
works to set sequencing. For typical connections to Intel
CPUs, no external sequencing is required.
The backup-battery input (BKBT) provides backup
power for V7 when V1 is disabled. Normally, a primary
or rechargeable backup battery is connected to this
pin. If a backup battery is not used, then BKBT should
connect to IN through a diode or external regulator. See
the Backup-Battery Configurations section for informa-
tion on how to use BKBT and V7.
An I
REG3 and REG6. The serial interface operates when IN
exceeds the 2.40V UVLO threshold and at least one of
ON1–ON6 is asserted. The serial interface is shut down
to minimize off-current drain when no regulators are
enabled.
The serial interface consists of a serial data line (SDA)
and a serial clock line (SCL). Standard I
write-byte commands are used. Figure 4 shows a tim-
ing diagram for the I
slave-only device, relying upon a master to generate a
clock signal. The master (typically a microprocessor)
initiates data transfer on the bus and generates SCL to
permit data transfer. A master device communicates to
the MAX8588 by transmitting the proper address fol-
lowed by the 8-bit data code (Table 2). Each transmit
sequence is framed by a START (A) condition and a
STOP (L) condition. Each word transmitted over the bus
is 8 bits long and is always followed by an acknowl-
edge clock pulse.
Table 2 shows the serial data codes used to program
V3 and V6. The default power-up voltage for V3 is 1.3V
and for V6 is 0V.
2
C-compatible, two-wire serial interface controls
2
C protocol. The MAX8588 is a
Connection to Processor
and Power Sequencing
Q
Backup-Battery Input
PMIC with
Serial Interface
2
C-compatible
21