ISL97644IRZ-TK Intersil, ISL97644IRZ-TK Datasheet

no-image

ISL97644IRZ-TK

Manufacturer Part Number
ISL97644IRZ-TK
Description
IC REG BOOST LDO VON VCOM 24-QFN
Manufacturer
Intersil
Datasheet

Specifications of ISL97644IRZ-TK

Applications
LCD Monitor, Notebook Display
Current - Supply
1mA
Voltage - Supply
3 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
24-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Boost + LDO + V
The ISL97644 represents an integrated DC/DC regulator for
monitor and notebook applications with screen sizes up to
20”. The device integrates a boost converter for generating
A
performance V
The boost converter features a 2.6A FET and has user
programmable soft-start and compensation. With efficiencies
up to 92%, the A
The logic LDO includes a 350mA FET for driving the low
voltage needed by the external digital circuitry.
The V
High and low levels are programmable, as well as discharge
rate and timing.
The integrated V
capability. With 30MHz bandwidth and 50V/µs slew rate, the
V
100mA continuous output current.
Pinout
VDD
COM
, a V
ON
VGH_M
amplifier is capable of driving 400mA peaks, and
VDD_1
VDD_2
VDPM
VFLK
GND
slice circuit can control gate voltages up to 30V.
ON
slice circuit, an integrated logic LDO and a high
1
2
3
4
5
6
COM
VDD
COM
24
7
amplifier.
is user selectable from 7V to 20V.
features high speed and drive
(24 LD 4x4 QFN)
23
8
ON
TOP VIEW
ISL97644
22
®
9
Slice + V
1
10
21
11
20
Data Sheet
12
19
COM
18
17
16
15
14
13
LX
VIN_2
FREQ
COMP
SS
VIN_1
1-888-INTERSIL or 1-888-468-3774
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Features
• 3V to 5.5V Input
• 2.6A Integrated Boost for Up to 20V A
• Integrated V
• 350mA V
• 600kHz/1.2MHz f
• V
• UV and OT Protection
• 24 Ld 4x4 QFN
• Pb-Free (RoHS Compliant)
Applications
• LCD Monitors (15”+)
• Notebook Display (up to 16”)
Ordering Information
ISL97644IRZ
ISL97644IRZ-T*
ISL97644IRZ-TK* 97644IRZ -40 to +85 24 Ld 4x4 QFN
*Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets; molding compounds/die attach
materials and 100% matte tin plate PLUS ANNEAL - e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
PART NUMBER
December 14, 2007
- 2.5V, 2.85V, 3.3V Output Voltage Selectable
- 30MHz BW
- 50V/µs SR
- 400mA Peak Output Current
COM
(Note)
All other trademarks mentioned are the property of their respective owners.
Amplifier
|
LOGIC
Intersil (and design) is a registered trademark of Intersil Americas Inc.
ON
Copyright Intersil Americas Inc. 2006, 2007. All Rights Reserved
MARKING
97644IRZ -40 to +85 24 Ld 4x4 QFN L24.4x4D
97644IRZ -40 to +85 24 Ld 4x4 QFN
LDO
Slice
PART
S
RANGE
TEMP.
(°C)
Tape & Reel
Tape & Reel
PACKAGE
VDD
(Pb-Free)
ISL97644
FN9228.1
L24.4x4D
L24.4x4D
DWG. #
PKG.

Related parts for ISL97644IRZ-TK

ISL97644IRZ-TK Summary of contents

Page 1

... Ordering Information PART NUMBER (Note) 19 ISL97644IRZ LX 18 ISL97644IRZ-T* VIN_2 17 ISL97644IRZ-TK* 97644IRZ - 4x4 QFN FREQ 16 COMP *Please refer to TB347 for details on reel specifications. 15 NOTE: These Intersil Pb-free plastic packaged products employ SS 14 special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination ...

Page 2

Pin Descriptions PIN NUMBER PIN NAME 1 GND 2 VGH_M 3 VFLK 4 VDPM 5 VDD_1 6 VDD_2 7 OUT 8 NEG 9 POS 10 AGND 11 ADJ 12 LDO_OUT 13 VIN_1 COMP 16 FREQ 17 VIN_2 ...

Page 3

... T = +70° .1.34W +85° .0.98W +100° .0.61W A Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp = ENABLE = 5V, VDD1 = VDD2 = 14V, VGH = 25V, AVDD = 10V, T IN2 TEST CONDITION See separate LDO specifications ENABLE = 0V ENABLE = 5V, LX not switching, LDO not loaded V Rising IN2 ...

Page 4

Electrical Specifications IN1 Unless Otherwise Noted. (Continued) SYMBOL PARAMETER V Feedback Voltage ( Input Bias Current FB R Switch On Resistance DS(ON) EFF Peak Efficiency I Switch Current Limit LIM D Max ...

Page 5

Electrical Specifications IN1 Unless Otherwise Noted. (Continued) SYMBOL PARAMETER I Output Short Circuit Current SC SR Slew Rate BW Gain Bandwidth GATE PULSE MODULATOR VGH VGH Voltage I VGH Input Current VGH V VDD1 Voltage DD1 I ...

Page 6

I Typical Performance Curves 100 OSC 200 400 600 IA (mA) VDD FIGURE 1. A EFFICIENCY vs IA VDD 10.5 10.45 A 150mA VDD 10.4 10.35 10.3 ...

Page 7

Typical Performance Curves CE = 1pF 100k VGH_M VFLK FIGURE 7. GPM CIRCUIT WAVEFORM CE = 10pF 100k VGH_M VFLK FIGURE 9. GPM CIRCUIT WAVEFORM INPUT SIGNAL OUTPUT SIGNAL FIGURE 11. V RISING SLEW RATE COM ...

Page 8

Block Diagram FREQ OSCILLATION GENERATOR SLOPE COMPENSATION COMP - FB + REFERENCE START-UP AND GENERATOR FAULT CONTROL ENABLE LDO CONTROLLER V IN1 OUT VFLK VGH 8 ISL97644 SUMMING AMPLIFIER LOGIC + - GPM CIRCUIT VGH_M CE RE FIGURE 13. ISL97644 ...

Page 9

Typical Application Diagram V IN VIN2 C1 22µF C3 2.2nF COMP R5 10k C4 SS 10nF ENABLE FREQ- VDPM VFLK C5 470P 130k R3 2k POS A VDD C11 1µF NEG- R7 80k OUT V COM +4.0V ...

Page 10

Operation The boost converter is a current mode PWM converter operating at either a 650kHz or 1.2MHz. It can operate in both discontinuous conduction mode (DCM) at light load and continuous mode (CCM). In continuous current mode, current flows continuously ...

Page 11

... ADJ pin is floating, the output voltage is set to 2.85V, and when ADJ pin is connected to LDO_OUT pin, the output voltage is set to 2.5V. in the equation above assumes the OUT SIZE MFG PART NUMBER 1210 TDK C3225X7R1E106M 1210 Murata GRM32DR61E106K . VDD LX FB Intersil ISL97644 OUTPUT VOLTAGE APPLICATIONS December 14, 2007 A VDD FN9228.1 ...

Page 12

The efficiency of LDO is depended on the difference between input voltage and output voltage, as well as the output current: η × – V IN1 LDO_OUT LDO_OUT The less difference between ...

Page 13

Low to high transition is determined primarily by the switch resistance and the external capacitive load. High to low transition is more complex. Take the case where the block is already enabled (VDPM is H). When VFLK is H, pin ...

Page 14

... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...

Page 15

Package Outline Drawing L24.4x4D 24 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 2, 10/06 4.00 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW ( TYP ) ( TYPICAL RECOMMENDED LAND PATTERN 15 ISL97644 ...

Related keywords