ISL97644IRZ-TK Intersil, ISL97644IRZ-TK Datasheet - Page 12

• Manufacturer Part Number: ISL97644IRZ-TK
• Description: IC REG BOOST LDO VON VCOM 24-QFN
• Manufacturer: Intersil

Specifications of ISL97644IRZ-TK

• Applications: LCD Monitor, Notebook Display
• Current - Supply: 1mA
• Voltage - Supply: 3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The efficiency of LDO is depended on the difference
between input voltage and output voltage, as well as the
output current:
The less difference between input and output voltage, the
higher efficiency it is. The minimum dropout voltage of LDO
of ISL97644 is 300mV.
The ceramic capacitors are recommended for the LDO input
and output capacitor. Larger capacitors help reduce noise
and deviation during transient load change.
η %
( )
=
(
V
IN1
–
V
LDO_OUT
) I
×
VGH_M
12
LDO_OUT
VDD1
VFLK
RE
CE
FIGURE 16. GATE PULSE MODULATOR CIRCUIT BLOCK DIAGRAM
×
100%
VGH
+
-
200µA
(EQ. 7)
x240
ISL97644
CONTROL AND
Gate Pulse Modulator Circuit
The gate pulse modulator circuit functions as a three way
multiplexer, switching VGHM between ground, VDD1 and
VGH. Voltage selection is provided by digital inputs VDPM
(enable) and VFLK (control). High to low delay and slew
control is provided by external components on pins CE and
RE, respectively. A block diagram of the gate pulse
modulator circuit is shown in Figure 16.
When VDPM is LOW, the block is disabled and VGHM is
grounded. When VDPM is HIGH, the output is determined
by VFLK. When VFLK goes high, VGHM is pulled to VGH by
a 70Ω switch. When VFLK goes low, there is a delay
controlled by capacitor CE, following which VGHM is driven
to VDD1, with a slew rate controlled by resistor RE. Note
that VDD1 is used only as a reference voltage for an
amplifier, thus does not have to source or sink a significant
DC current.
TIMING
+
-
-
EnGPM1
VREF
December 14, 2007
FN9228.1