NCP1562ADBR2G ON Semiconductor, NCP1562ADBR2G Datasheet - Page 17

• Manufacturer Part Number: NCP1562ADBR2G
• Description: IC CLAMP/RESET PWM CTLR 16-TSSOP
• Manufacturer: ON Semiconductor

Specifications of NCP1562ADBR2G

• Pwm Type: Voltage Mode
• Number Of Outputs: 2
• Frequency - Max: 1MHz
• Duty Cycle: 85%
• Voltage - Supply: 23.2 V ~ 100 V
• Buck: No
• Boost: Yes
• Flyback: Yes
• Inverting: Yes
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 16-TSSOP
• Frequency-max: 1MHz
• Topology: Flyback, Forward, Half-Bridge
• Output Voltage: 20 V
• Output Current: 2000 mA, 1000 mA
• Switching Frequency: 1000 KHz
• Duty Cycle (max): 85 %
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Fall Time: 10 ns
• Mounting Style: SMD/SMT
• Rise Time: 26 ns
• Synchronous Pin: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: NCP1562ADBR2G; NCP1562ADBR2GOSTR

auto re- - start) the NCP1562 after a cycle skip event is
detected. This can be easily achieved by adding an external
latch. Figures 35 and 36 show an implementation of an
integrated and a discrete latch, respectively. In general the
circuits work by pulling CSKIP to V
reaching V
turn on threshold of the latch. The external latch is cleared
by bringing the UVOV voltage below V
V
output buffer from ON Semiconductor’s MiniGatet
family. The enable (OE) and output (OUTY) terminals are
connected to CSKIP and the V
connected to V
impedance mode when OE is low. Once a continuous
current limit condition is detected, the CSKIP timer is
enabled and CSKIP begins charging. Once the voltage on
CSKIP reaches the enable threshold of the buffer, the
output of the buffer is pulled to V
timer. The OE threshold of the buffer is typically 1.5 V.
REF
In some instances it may be desired to latch (instead of
The latch in Figure 38 consists of a TTL level tri- - state
V
CSKIP
CSKIP
V
.
REF
Figure 38. External Latch Implemented using
Figure 39. External Latch Implemented using
REF
ON Semiconductor’s MiniGatet Buffer
Discrete N and P- -Channel MOSFETs
C
C
CSKIP(valley)
REF
REF
REF
BSS84L
M2
. The output of the buffer is in a high
C
CSKIP
C
once the CSKIP voltage reaches the
OUTY
CSKIP
24.9 kΩ
V
OE
CC
REF
M1
CC
REF
, latching the CSKIP
and INA pins are
MC74VHC1GT126
, preventing it from
R
UV
pull- -up
INA
and disabling
2N7002L
http://onsemi.com
17
MOSFETs is shown in Figure 39. The latch is enabled once
the CSKIP voltage reaches the threshold of M1. Once M1
turns on, it pulls low the gate of M2. CSKIP is then pulled
to V
R
charges. This will cause the controller to latch during initial
power- - up. In this particular implementation the turn on
threshold of M1 is 2 V and R
Leading Edge Blanking
caused by the power switch transitions. The current signal
is usually filtered using an RC low–pass filter to avoid
premature triggering of the current limit circuit. However,
the low pass filter will inevitably change the shape of the
current pulse and also add cost and complexity. The
NCP1562 uses LEB circuitry that blocks out the first 70 ns
(typ) of each current pulse. This removes the leading edge
spikes without altering the current waveform. The blanking
period is disabled during soft- - start as the blanking period
may be longer than the startup duty cycle. It is also disabled
if the output of the Saturation Comparator is low, indicating
that the output is not yet in regulation. This occurs during
power up or during an output overload condition.
Supply Voltage and Startup Circuit
need for external startup components. In addition, this
regulator increases the efficiency of the supply as it uses no
power when in the normal mode of operation, but instead
uses power supplied by an auxiliary winding. The
NCP1562 incorporates an optimized startup circuit that
reduces the requirement of the supply capacitor,
particularly important in size constrained applications.
source that supplies current from the input line voltage
(V
startup current (I
regulator is disabled and the outputs are enabled if there are
no UV, OV, cycle skip or thermal shutdown faults. The
startup regulator remains disabled until the lower voltage
threshold (V
the startup circuit is enabled. If the bias current requirement
out of C
discharge until reaching the lower voltage threshold
(V
outputs are disabled. Once the outputs are disabled, the bias
current of the IC is reduced, allowing V
up. This mode of operation allows a dramatic reduction in
the size of C
needs to be stored by C
known as Dynamic Self Supply (DSS). Figure 40 shows the
relationship between V
UV. As shown in Figure 40, the outputs are not enabled
until the UV fault is removed and V
pull- - up
A latch implemented using discrete N and P- - channel
The current sense signal is prone to leading edge spikes
The NCP1562 internal startup regulator eliminates the
The startup regulator consists of a constant current
Once C
AUX(off2)
in
) to the supply capacitor on the V
REF
AUX
by M2. It is important to size R
is too big, it will not keep M2 off while V
AUX
) of 7.0 V. Upon reaching V
AUX(off1)
AUX
is greater than the startup current, V
is charged to 10.3 V (V
start
as not all the power required for startup
) is typically 10 mA.
) of 8.0 V is reached. Once reached,
AUX(on)
AUX
pull- - up
. This mode of operation is
, V
AUX(off1)
AUX
is sized to 24.9 k.
AUX
AUX(on)
AUX
pull- - up
reaches V
pin (C
, V
to charge back
AUX(off2)
AUX(off2)
), the startup
correctly. If
AUX
AUX
AUX(on)
). The
, the
will
REF
and
.