NCP1562ADBR2G ON Semiconductor, NCP1562ADBR2G Datasheet - Page 22

• Manufacturer Part Number: NCP1562ADBR2G
• Description: IC CLAMP/RESET PWM CTLR 16-TSSOP
• Manufacturer: ON Semiconductor

Specifications of NCP1562ADBR2G

• Pwm Type: Voltage Mode
• Number Of Outputs: 2
• Frequency - Max: 1MHz
• Duty Cycle: 85%
• Voltage - Supply: 23.2 V ~ 100 V
• Buck: No
• Boost: Yes
• Flyback: Yes
• Inverting: Yes
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 16-TSSOP
• Frequency-max: 1MHz
• Topology: Flyback, Forward, Half-Bridge
• Output Voltage: 20 V
• Output Current: 2000 mA, 1000 mA
• Switching Frequency: 1000 KHz
• Duty Cycle (max): 85 %
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Fall Time: 10 ns
• Mounting Style: SMD/SMT
• Rise Time: 26 ns
• Synchronous Pin: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: NCP1562ADBR2G; NCP1562ADBR2GOSTR

charging of the RTCT Ramp. In this period the oscillator
accepts an external SYNC pulse. If no pulse is detected
upon reaching the peak of the RTCT Ramp, a 100 ns SYNC
pulse is generated. The SYNC pulse is generated by
internally pulling the SYNC pin to V
of the SYNC pin is typically 4.3 V. Once the 100 ns timer
expires, the pin goes back into a high impedance mode and
an external resistor is required for pulldown as shown in
Figure 49.
capacitance and external pulldown resistor. The maximum
source current of the SYNC pin is 1.0 mA. The resistor is
sized to allow the SYNC pin to discharge before the start
of the next cycle.
the internal pulse is generated, the controller enters the
slave mode of operation. Once operation in slave mode
commences, C
upper threshold is increased to 4.0 V.
before reaching the R
upper threshold is reset back to 3.0 V and the converter
reverts to operation in master mode. To guarantee the
converter stays in slave mode, the minimum clock period
of the master controller has to be less than the R
time from 2.0 V to 4.0 V.
SYNC pins together. The first device that generates a sync
pulse during powerup becomes the master. A diode
connected as shown in Figure 50 can be used to
permanently set one controller as the master. The diode
prevents the master from receiving the SYNC pulse of the
slave controller.
The SYNC pin is in a high impedance mode during the
The slew rate of the sync pin is determined by the pin
If an external pulse is received on the SYNC pin before
If a controller in slave mode does not receive a sync pulse
Two NCP1562’s are synchronized by connecting their
T
Figure 49. SYNC Pulse
begins discharging and the R
SYNC
V
RTCT
T
REF
C
C
T
T
Ramp peak voltage (4.0 V), the
R
R
T
SYNC
REF
. The peak voltage
T
T
C
C
T
T
charge
http://onsemi.com
Ramp
22
5.0 V Reference
is a buffered version of the internal reference. The 5.0 V
reference is biased directly from V
to 5.0 mA. Load regulation is 50 mV and line regulation is
100 mV within the specified operating range.
The capacitor is used for compensation of the internal
regulator and high frequency noise filtering. The capacitor
should be placed across the V
applications a 0.1 mF will suffice. A bigger capacitor may
be required to reduce the voltage ripple caused by the
oscillator current. The recommended capacitor range is
between 0.047 mF and 1.0 mF.
V
Otherwise, the reference is enabled once the UV fault is
removed and V
enabled, the reference is disabled after the soft- - stop
sequence is complete if the UV fault is still present. If the
UV fault is removed before soft- - stop is complete, the
reference is not disabled.
Application Information
demonstration board and an application note to facilitate
design of the NCP1562 and reduce development cycle
time. All the tools can be downloaded or ordered at
www.onsemi.com.
determine most of the system parameters of an active
clamp forward converter. The tool evaluates the power and
active clamp stages as well as the frequency response of the
system. The tool is used to design a converter for a 48 V
telecom system. The converter delivers 100 W at 3.3 V.
The circuit schematic is shown in Figure 51. The converter
design is described in Application Note AND8273/D.
CONTROLLER
AUX
The NCP1562 has a precision 5.0 V reference output. It
It is required to bypass the reference with a capacitor.
During powerup, the 5.0 V reference is enabled once
Once a UV fault is detected after the reference has been
ON Semiconductor provides an electronic design tool, a
The electronic design tool allows the user to easily
MASTER
reaches V
Figure 50. Master- -Slave Configuration
AUX
R
AUX(on)
SYNC
SYNC1
reaches V
and a UV fault is not present.
AUX(on)
REF
AUX
and GND pins. In most
R
SYNC
SYNC2
.
and it can supply up
CONTROLLER
SLAVE