NCP1562ADBR2G ON Semiconductor, NCP1562ADBR2G Datasheet - Page 3

• Manufacturer Part Number: NCP1562ADBR2G
• Description: IC CLAMP/RESET PWM CTLR 16-TSSOP
• Manufacturer: ON Semiconductor

Specifications of NCP1562ADBR2G

• Pwm Type: Voltage Mode
• Number Of Outputs: 2
• Frequency - Max: 1MHz
• Duty Cycle: 85%
• Voltage - Supply: 23.2 V ~ 100 V
• Buck: No
• Boost: Yes
• Flyback: Yes
• Inverting: Yes
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 16-TSSOP
• Frequency-max: 1MHz
• Topology: Flyback, Forward, Half-Bridge
• Output Voltage: 20 V
• Output Current: 2000 mA, 1000 mA
• Switching Frequency: 1000 KHz
• Duty Cycle (max): 85 %
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Fall Time: 10 ns
• Mounting Style: SMD/SMT
• Rise Time: 26 ns
• Synchronous Pin: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: NCP1562ADBR2G; NCP1562ADBR2GOSTR

PIN FUNCTION DESCRIPTION
Pin
10
11
12
13
14
1
2
3
4
5
6
7
8
9
Symbol
CSKIP
PGND
UVOV
SYNC
OUT2
R
GND
V
V
V
CS
SS
FF
T
REF
t
EA
D
in
C
T
Connect the input line voltage directly to this pin to enable the internal startup regulator. A constant
current source supplies current from this pin to the capacitor connected to the V
need for a startup resistor. The charge current is typically 10 mA. Maximum input voltage is 100 V.
Input supply voltage is scaled down and sampled by means of a resistor divider. The same pin is used
for both undervoltage (UV) and overvoltage (OV) detection using a novel architecture (patent pending).
The minimum and maximum input supply voltage thresholds are adjusted independently. A UV
condition exists if the UVOV voltage is below 2.0 V and an OV condition exists if the UVOV voltage
exceeds 3.0 V. The undervoltage threshold is trimmed during manufacturing to obtain 3% accuracy
allowing a tighter power stage design. Both the UV and OV detectors have a 100 mV hysteresis.
An external R- -C divider from the input line generates the Feedforward Ramp. This ramp is used by the
PWM comparator to set the duty cycle, thus providing direct line regulation. An internal pulldown
transistor discharges the external capacitor every cycle. Once discharged, the capacitor is effectively
grounded until the next cycle begins.
Overcurrent sense input. If the CS voltage exceeds 0.2 V (or 0.5 V in the NCP1562B) the converter
operates in cycle- -by- -cycle current limit. Once a current limit pulse is detected, the cycle skip timer is
enabled. Internal leading edge blanking pulse prevents nuisance triggering during normal operation.
The leading edge blanking is disabled during soft- -start and output overload conditions to improve the
response to faults.
Control circuit ground. All control and timing components that connect to GND should have the shortest
loop possible to this pin to improve noise immunity.
An external R
The maximum operating frequency is 1.0 MHz. A sawtooth Ramp between 2.0 V and 3.0 V is
generated by sequentially charging and discharging C
accurately controlled to provide precise control of the duty cycle and frequency. The outputs are
disabled during the C
Proprietary bidirectional frequency synchronization architecture allows two NCP1562 devices to
synchronize together. The lower frequency device becomes the slave. It can also synchronize to an
external signal.
Precision 5.0 V reference. Maximum output current is 5.0 mA. It is required to bypass the reference
with a capacitor. The recommended capacitance range is between 0.047 mF and 1.0 mF.
The error signal from an external error amplifier is fed to this input and compared to the Feedforward
Ramp. A series diode and resistor offset the voltage on this pin before it is applied to the PWM
Comparator inverting input. An internal pullup resistor allows direct connection to an optocoupler.
A 10 mA current source charges the external capacitor connected to this pin. Duty cycle is limited
during startup by comparing the voltage on this pin to the Feedforward Ramp. Under steady state
conditions, the SS voltage is approximately 3.8 V. Once a UV, OV, overtemperature or cycle skip fault
is detected, the SS capacitor is discharged in a controlled manner with a 100 mA current source. The
duty cycle is then slowly reduced until reaching 0%.
An external resistor between this pin and GND sets the overlap time delay between OUT1 and OUT2
transitions.
The converter is disabled if a continuous overcurrent condition exists. The time to determine the fault
and the time the converter is disabled are programmed by the capacitor (C
The cycle skip timer is enabled after a current limit fault is detected. Once enabled, C
with a 100 mA source. If the overcurrent fault is removed before entering the soft- -stop mode, the
capacitor is discharged with a 10 mA source. Once C
soft- -stop mode and C
C
discharges to 0 V. Otherwise, it starts charging from 0.5 V, setting up a hiccup mode operation.
Secondary output of the PWM Controller. It can be used to drive an active clamp/reset switch, a
synchronous rectifier topology, or both. OUT2 has an adjustable leading and trailing edge overlap delay
against OUT1. OUT2 has source and sink resistances of 12 Ω (typ.). OUT2 is designed to handle up
to 1.0 A.
Ground connection for OUT1 and OUT2. Tie to the power stage return with a short loop.
CSKIP
reaches 0.5 V. If the condition resulting in overcurrent is cleared during this phase, C
T
- -C
T
divider from V
T
http://onsemi.com
CSKIP
discharge time.
is discharged with a 10 mA source. The converter is re- -enabled once
3
REF
sets the operating frequency and maximum duty cycle of OUT1.
Description
CSKIP
T
. The peak and valley of the Ramp are
reaches 3.0 V, the converter enters a
CSKIP
AUX
) connected to this pin.
pin, eliminating the
CSKIP
is charged
CSKIP