IDT89HPES12T3G2ZABCG8 IDT, Integrated Device Technology Inc, IDT89HPES12T3G2ZABCG8 Datasheet

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IDT89HPES12T3G2ZABCG8

Manufacturer Part Number
IDT89HPES12T3G2ZABCG8
Description
IC PCI SW 12LANE 3PORT 324-BGA
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of IDT89HPES12T3G2ZABCG8

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
89HPES12T3G2ZABCG8

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Part Number:
IDT89HPES12T3G2ZABCG8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Device Overview
Express® switching solutions. The PES12T3G2 is a 12-lane, 3-port
Gen2 peripheral chip that performs PCI Express Base switching with a
feature set optimized for high performance applications such as servers,
storage, and communications/networking. It provides connectivity and
switching functions between a PCI Express upstream port and two
downstream ports and supports switching between downstream ports.
Features
Block Diagram
© 2010 Integrated Device Technology, Inc.
The 89HPES12T3G2 is a member of IDT’s PRECISE™ family of PCI
– Twelve 5 Gbps Gen2 PCI Express lanes
– Three switch ports
– Low latency cut-through switch architecture
– Support for Max Payload Size up to 2048 bytes
– One virtual channel
– Eight traffic classes
– PCI Express Base Specification Revision 2.0 compliant
– Automatic per port link width negotiation to x4, x2 or x1
– Automatic lane reversal on all ports
– Automatic polarity inversion
– Ability to load device configuration from serial EEPROM
High Performance PCI Express Switch
Flexible Architecture with Numerous Configuration Options
• One x4 upstream port
• Two x4 downstream ports
Multiplexer / Demultiplexer
Transaction Layer
Data Link Layer
(Port 0)
SerDes
Logical
Layer
Phy
Frame Buffer
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
®
12-Lane 3-Port
Gen2 PCI Express® Switch
3-Port Switch Core / 12 PCI Express Lanes
Route Table
Figure 1 Internal Block Diagram
Multiplexer / Demultiplexer
Transaction Layer
Data Link Layer
1 of 30
(Port 2)
SerDes
Logical
Layer
Phy
Arbitration
– PCI compatible INTx emulation
– Bus locking
– Incorporates on-chip internal memory for packet buffering and
– Integrates twelve 5 Gbps embedded SerDes with 8b/10b
– Internal end-to-end parity protection on all TLPs ensures data
– Supports ECRC and Advanced Error Reporting
– Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O
– Compatible with Hot-Plug I/O expanders used on PC mother-
– Supports Hot-Swap
Legacy Support
Highly Integrated Solution
Reliability, Availability, and Serviceability (RAS) Features
Port
• Receive equalization (RxEQ)
queueing
encoder/decoder (no separate transceivers needed)
integrity even in systems that do not implement end-to-end
CRC (ECRC)
boards
Multiplexer / Demultiplexer
Scheduler
Transaction Layer
Data Link Layer
SerDes
(Port 4)
Logical
Layer
Phy
89HPES12T3G2
September 13, 2010
Data Sheet
DSC 6930

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IDT89HPES12T3G2ZABCG8 Summary of contents

Page 1

Device Overview The 89HPES12T3G2 is a member of IDT’s PRECISE™ family of PCI Express® switching solutions. The PES12T3G2 is a 12-lane, 3-port Gen2 peripheral chip that performs PCI Express Base switching with a feature set optimized for high performance ...

Page 2

IDT 89HPES12T3G2 Data Sheet ◆ Power Management – Utilizes advanced low-power design techniques to achieve low typical power consumption – Support PCI Express Power Management Interface specifica- tion (PCI-PM 1.2) – Supports PCI Express Active State Power Management (ASPM) link ...

Page 3

IDT 89HPES12T3G2 Data Sheet As shown in Figure 3, the master and slave SMBuses may be used in a unified or split configuration. In the unified configuration, shown in Figure 3(a), the master and slave SMBuses are tied together and ...

Page 4

IDT 89HPES12T3G2 Data Sheet Pin Description The following tables list the functions of the pins provided on the PES12T3G2. Some of the functions listed may be multiplexed onto the same pin. The active polarity of a signal is defined using ...

Page 5

IDT 89HPES12T3G2 Data Sheet Signal GPIO[0] GPIO[1] GPIO[2] GPIO[3] GPIO[4] GPIO[5] GPIO[6] GPIO[7] GPIO[11] Type Name/Description I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P2RSTN Alternate function pin type: ...

Page 6

IDT 89HPES12T3G2 Data Sheet Signal CCLKDS CCLKUS MSMBSMODE PERSTN RSTHALT SWMODE[2:0] Signal JTAG_TCK JTAG_TDI Type Name/Description I Common Clock Downstream. The assertion of this pin indicates that all downstream ports are using the same clock source as that provided to ...

Page 7

IDT 89HPES12T3G2 Data Sheet Signal JTAG_TDO JTAG_TMS JTAG_TRST_N Signal REFRES0 REFRES2 REFRES4 V CORE PEA DD V PEHA DD V PETA Type Name/Description O JTAG Data Output. This is the serial data ...

Page 8

IDT 89HPES12T3G2 Data Sheet Pin Characteristics Note: Some input pads of the PES12T3G2 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if ...

Page 9

IDT 89HPES12T3G2 Data Sheet Function SerDes Reference REFRES0 Resistors REFRES2 REFRES4 1. Internal resistor values under typical operating conditions are 92K Ω for pull-up and 90K Ω for pull-down. 2. All receiver pins set the DC common mode voltage to ...

Page 10

IDT 89HPES12T3G2 Data Sheet Logic Diagram — PES12T3G2 Reference Clocks Reference Clock Frequency Selection PCI Express Switch SerDes Input Port 0 PCI Express Switch SerDes Input Port 2 PCI Express Switch SerDes Input Port 4 Master SMBus Interface Slave SMBus ...

Page 11

IDT 89HPES12T3G2 Data Sheet System Clock Parameters Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 13 and 15. Parameter Description Refclk Input reference clock frequency range FREQ T Rising edge rate C-RISE ...

Page 12

IDT 89HPES12T3G2 Data Sheet Parameter T Maximum time to transition to a valid Idle after sending TX-IDLE-SET-TO-IDLE an Idle ordered set T Maximum time to transition from valid idle to diff data TX-IDLE-TO-DIFF- DATA T Transmitter data skew between any ...

Page 13

IDT 89HPES12T3G2 Data Sheet Signal JTAG JTAG_TCK 1 JTAG_TMS , JTAG_TDI JTAG_TDO JTAG_TRST_N 1. The JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N changes from Otherwise, a ...

Page 14

IDT 89HPES12T3G2 Data Sheet Recommended Operating Supply Voltages Symbol V CORE Internal logic supply DD V I/O I/O supply except for SerDes LVPECL/CML PEA PCI Express Analog Power PEHA PCI Express Analog High Power ...

Page 15

IDT 89HPES12T3G2 Data Sheet Power Consumption Typical power is measured under the following conditions: 25°C Ambient, 35% total link usage on all ports, typical voltages defined in Table 13 (and also listed below). Maximum power is measured under the following ...

Page 16

IDT 89HPES12T3G2 Data Sheet DC Electrical Characteristics Values based on systems running at recommended supply voltages, as shown in Table 13. Note: See Table 8, Pin Characteristics, for a complete I/O listing. I/O Type Parameter Description Serial Link PCIe Transmit ...

Page 17

IDT 89HPES12T3G2 Data Sheet I/O Type Parameter Description Serial Link PCIe Receive (cont.) V Differential input voltage (peak-to- RX-DIFFp-p peak) RL Receiver Differential Return Loss RX-DIFF RL Receiver Common Mode Return RX-CM Loss Z Differential input impedance (DC) RX-DIFF-DC Z ...

Page 18

IDT 89HPES12T3G2 Data Sheet Package Pinout — 324-BGA Signal Pinout for PES12T3G2 The following table lists the pin numbers and signal names for the PES12T3G2 device. Pin Function Alt Pin A1 V B17 B18 SS A3 PE0RN00 ...

Page 19

IDT 89HPES12T3G2 Data Sheet Pin Function Alt Pin H11 V CORE K13 DD H12 V K14 SS H13 V K15 SS H14 V PEHA K16 DD H15 V CORE K17 DD H16 PE4TN01 K18 H17 H18 PE4RN01 ...

Page 20

IDT 89HPES12T3G2 Data Sheet Pin Function Alt Pin U1 V U10 U11 SS U3 SSMBCLK U12 U4 SSMBADDR_3 U13 U5 V U14 SS U6 MSMBCLK U15 U7 MSMBADDR_1 U16 U8 V PEA U17 U18 ...

Page 21

IDT 89HPES12T3G2 Data Sheet Power Pins V Core DD B14 D8 D9 D12 E5 E10 E13 F4 F7 F12 F14 H11 H15 J5 J9 J12 V Core V I K10 ...

Page 22

IDT 89HPES12T3G2 Data Sheet Ground Pins A11 A14 B12 B13 B15 C4 C9 C15 D1 D7 D13 E17 H10 ...

Page 23

IDT 89HPES12T3G2 Data Sheet Signals Listed Alphabetically Signal Name CCLKDS CCLKUS GPIO_00 GPIO_01 GPIO_02 GPIO_03 GPIO_04 GPIO_05 GPIO_06 GPIO_07 GPIO_11 JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N MSMBADDR_1 MSMBADDR_2 MSMBADDR_3 MSMBADDR_4 MSMBCLK MSMBDAT MSMBSMODE No Connection PE0RN00 PE0RN01 PE0RN02 I/O Type Location ...

Page 24

IDT 89HPES12T3G2 Data Sheet Signal Name PE0RN03 PE0RP00 PE0RP01 PE0RP02 PE0RP03 PE0TN00 PE0TN01 PE0TN02 PE0TN03 PE0TP00 PE0TP01 PE0TP02 PE0TP03 PE2RN00 PE2RN01 PE2RN02 PE2RN03 PE2RP00 PE2RP01 PE2RP02 PE2RP03 PE2TN00 PE2TN01 PE2TN02 PE2TN03 PE2TP00 PE2TP01 PE2TP02 PE2TP03 PE4RN00 PE4RN01 PE4RN02 PE4RN03 PE4RP00 ...

Page 25

IDT 89HPES12T3G2 Data Sheet Signal Name PE4RP03 PE4TN00 PE4TN01 PE4TN02 PE4TN03 PE4TP00 PE4TP01 PE4TP02 PE4TP03 PEREFCLKN0 PEREFCLKP0 PERSTN REFCLKM REFRES0 REFRES2 REFRES4 RSTHALT SSMBADDR_1 SSMBADDR_2 SSMBADDR_3 SSMBADDR_5 SSMBCLK SSMBDAT SWMODE_0 SWMODE_1 SWMODE_2 V CORE PEA, V ...

Page 26

IDT 89HPES12T3G2 Data Sheet PES12T3G2 Pinout — Top View ...

Page 27

IDT 89HPES12T3G2 Data Sheet PES12T3G2 Package Drawing — 324-Pin BC324/BCG324 September 13, 2010 ...

Page 28

IDT 89HPES12T3G2 Data Sheet PES12T3G2 Package Drawing — Page Two September 13, 2010 ...

Page 29

IDT 89HPES12T3G2 Data Sheet Revision History March 27, 2008: Initial publication of final data sheet. April 17, 2008: In Table 16, Thermal Specifications, revised values for October 28, 2008: Added ZB silicon to Ordering Information section. February 24, 2009: Revised ...

Page 30

IDT 89HPES12T3G2 Data Sheet Ordering Information NN A AAA NNAN Product Operating Device Product Family Family Voltage Detail Valid Combinations 89HPES12T3G2ZABC 324-ball BGA package, Commercial Temperature 89HPES12T3G2ZABCG 324-ball Green BGA package, Commercial Temperature 89HPES12T3G2ZBBC 324-ball BGA package, Commercial Temperature 89HPES12T3G2ZBBCG ...

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