IDT72P51749L6BBI8 IDT, Integrated Device Technology Inc, IDT72P51749L6BBI8 Datasheet - Page 11

• Manufacturer Part Number: IDT72P51749L6BBI8
• Description: IC FLOW CTRL 36BIT 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72P51749L6BBI8

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72P51749L6BBI8

PIN DESCRIPTIONS (CONTINUED)
IDT72P51749/72P51759/72P51769 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES
(128 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648, 2,359,296, and 4,718,592
bits
FF/IR
(P8)
FM
(K16)
FSTR
(R4)
FSYNC
(R3)
FWFT
(R11)
FXI
(T2)
FXO
(T3)
ID[2:0]
(ID2-C9
ID1-A10
ID0-B10)
Symbol &
(1)
Pin No.
(1)
Full Flag/
Input Ready
Flag Mode
PAFn Flag Bus HSTL-LVTTL If direct operation of the PAFn bus has been selected, the FSTR input is used in conjunction with WCLK
Strobe
PAFn Bus Sync HSTL-LVTTL FSYNC is an output from the multi-queue device that provides a synchronizing pulse for the PAFn bus
First Word Fall
Through
PAFn Bus
Expansion In
PAFn Bus
Expansion Out
Device ID Pins HSTL-LVTTL For the 128Q multi-queue device the WRADD and RDADD address busses are 8 bits wide. When a queue
Name
HSTL-LVTTL This pin provides the full flag output for the active Queue, that is, the queue selected on the input port
HSTL-LVTTL This pin is setup before a master reset and must not toggle during any device operation. The state of the
HSTL-LVTTL First word fall through (FWFT) or IDT Standard mode is selected during a Master Reset cycle. To select
HSTL-LVTTL The FXI input is used when multi-queue devices are connected in expansion configuration and Polled
HSTL-LVTTL FXO is an output that is used when multi-queue devices are connected in expansion configuration and
I/O TYPE
OUTPUT
OUTPUT
OUTPUT
INPUT
INPUT
INPUT
INPUT
INPUT
for write operations, (selected via WCLK, WRADD bus and WADEN). On the 3rd WCLK cycle after a queue
selection, this flag will show the status of the newly selected queue. Data can be written to this queue on
the next cycle provided FF is HIGH. This flag has High-Impedance capability, this is important during
expansion of devices, when the FF flag output of up to 2 devices may be connected together on a common
line. The device with a queue selected takes control of the FF bus, all other devices place their FF output
into High-Impedance. When a queue selection is made on the write port this output will switch from
High-Impedance control on the next WCLK cycle. This flag is synchronized to WCLK.
FM pin during Master Reset will determine whether the PAFn and PAEn flag busses operate in either Polled
or Direct mode. If this pin is HIGH the mode is Polled, if LOW then it will be Direct.
and the WRADD bus to select a status word of queues to be placed on to the PAFn bus outputs. A status
word addressed via the WRADD bus is selected on the rising edge of WCLK provided that FSTR is HIGH.
If Polled operations has been selected, FSTR should be tied inactive, LOW. Note, that a PAFn flag bus
selection cannot be made, (FSTR must NOT go active) until programming of the part has been completed
and SENO has gone LOW.
during Polled operation of the PAFn bus. During Polled operation each status word of queue status flags
is loaded on to the PAFn bus outputs sequentially based on WCLK. The first WCLK rising edge loads
status word 1 on to PAFn, the second WCLK rising edge loads status word 2 and so on. The fifth WCLK
rising edge will again load status word 1. During the WCLK cycle that status word 1 of a selected device
is placed on to the PAFn bus, the FSYNC output will be HIGH. For all other status words of that device,
the FSYNC output will be LOW.
FWFT mode assert the FWFT signal = HIGH, if FWFT = LOW during the master reset then IDT Standard
mode is selected.
PAFn bus operation has been selected . FXI of device ‘N’ connects directly to FXO of device ‘N-1’. The
FXI receives a token from the previous device in a chain. In single device mode the FXI input must be
tied LOW if the PAFn bus is operated in direct mode. If the PAFn bus is operated in polled mode the FXI
input must be connected to the FXO output of the same device. In expansion configuration the FXI of the
first device should be tied LOW, when direct mode is selected.
Polled PAFn bus operation has been selected . FXO of device ‘N’ connects directly to FXI of device ‘N+1’.
This pin pulses when device N has placed its final (4th) status word on to the PAFn bus with respect to
WCLK. This pulse (token) is then passed on to the next device in the chain ‘N+1’ and on the next WCLK
rising edge the first status word of device N+1 will be loaded on to the PAFn bus. This continues through
the chain and FXO of the last device is then looped back to FXI of the first device. The FSYNC output of
each device in the chain provides synchronization to the user of this looping event.
selection takes place the MSb of this 8 bit address bus are used to address the specific device (the 0-6
LSb’s are used to address the queue within that device). During write/read operations the MSb of the
address are compared to the device ID pins. In an eight device expansion configuration, the first device
in a chain of multi-queue’s (connected in expansion configuration), may be setup as ‘000' (this is referred
to as the Master Device), the second as ‘001’, however the ID does not have to match the device
order. In single device mode these pins should be setup as ‘000’ and the MSb of the WRADD and
RDADD address busses should be tied LOW. The ID[2:0] inputs setup a respective devices ID during
master reset. These ID pins must not toggle during any device operation. Note, the device selected
as the ‘Master’ must be ID ‘000’. In serial programming, the master device (ID 000) must be programmed
last.
11
Description
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 10, 2009