IDT72P51749L6BBI8 IDT, Integrated Device Technology Inc, IDT72P51749L6BBI8 Datasheet - Page 12

• Manufacturer Part Number: IDT72P51749L6BBI8
• Description: IC FLOW CTRL 36BIT 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72P51749L6BBI8

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72P51749L6BBI8

PIN DESCRIPTIONS (CONTINUED)
IDT72P51749/72P51759/72P51769 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES
(128 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648, 2,359,296, and 4,718,592 bits
IOSEL
(C8)
MAST
(K15)
MRS
(T9)
OE
(M14)
PAE
(P10)
PAEn/PRn
(PAE7-P11
PAE6-P12
PAE5-R12
PAE4-T12
PAE3-P13
PAE2-R13
PAE1-T13
PAE0-T14)
PAF
(R8)
PAFn
(PAF7-P7
PAF6-P6
PAF5-R6
PAF4-R7
PAF3-P5
PAF2-R5
PAF1-T5
PAF0-T4)
PKT
(J14)
Symbol &
Pin No.
(1)
(1)
IO Select
Master Device
Master Reset
Output Enable
Programmable
Almost-Empty
Flag
Programmable
Almost-Empty
Flag Bus/Packet
Ready Flag Bus
Programmable
Almost-Full Flag
Programmable
Almost-Full Flag
Bus
Packet Mode
Name
HSTL-LVTTL The state of this input at Master Reset determines whether a given device (within a chain of devices), is the
HSTL-LVTTL A master reset is performed by taking MRS from HIGH to LOW, to HIGH. Device programming is required
HSTL-LVTTL The Output enable signal is an Asynchronous signal used to provide three-state control of the multi-queue
HSTL-LVTTL This pin provides the Almost-Empty flag status for the Queue that has been selected on the output port
HSTL-LVTTL On the 128Q device the PAEn/PRn bus is 8 bits wide. During a Master Reset this bus is setup for either
HSTL-LVTTL This pin provides the Almost-Full flag status for the Queue that has been selected on the input port for
HSTL-LVTTL On the 128Q device the PAFn bus is 8 bits wide. At any one time this output bus provides PAF status
HSTL-LVTTL The state of this pin during a Master Reset will determine whether the part is operating in Packet mode
OUTPUT
OUTPUT
OUTPUT
OUTPUT
I/O TYPE
LVTTL
INPUT
INPUT
INPUT
INPUT
INPUT
This pin is used to select either HSTL or 2.5V LVTTL operation for the I/O. If HSTL or eHSTL I/O are
required then IOSEL should be tied HIGH (V
Master device or a Slave. If this pin is HIGH, the device is the master if it is LOW then it is a Slave. The
master device is the first to take control of all outputs after a master reset, all slave devices go to High-
Impedance, preventing bus contention. If a multi-queue device is being used in single device mode, this
pin must be set HIGH.
after master reset.
data output bus, Qout. If a device has been configured as a “Master” device, the Qout data outputs will
be in a Low Impedance condition if the OE input is LOW. If OE is HIGH then the Qout data outputs will be
in High Impedance. If a device is configured a “Slave” device, then the Qout data outputs will always be
in High Impedance until that device has been selected on the Read Port, at which point OE provides three-
state of that respective device.
for read operations, (selected via RCLK, RDADD and RADEN). This pin is LOW when the selected
Queue is almost-empty. This flag output may be duplicated on one of the PAEn bus lines. This flag is
synchronized to RCLK.
Almost Empty mode or Packet mode. This output bus provides PAE/PRn status of 8 queues (1 status word),
within a selected device, having a maximum of 16 status words. During Queue read/write operations
these outputs provide programmable empty flag status or packet ready status, in either direct or polled
mode. The mode of flag operation is determined during master reset via the state of the FM input.
This flag bus is capable of High-Impedance state, this is important during expansion of multi-queue devices.
During direct operation the PAEn/PRn bus is updated to show the PAE/PR status of a status word of queues
within a selected device. Selection is made using RCLK, ESTR and RDADD. During Polled operation
the PAEn/PRn bus is loaded with the PAE/PRn status of multi-queue flow-control status words sequentially
based on the rising edge of RCLK. PAE or PR operation is determined by the state of PKT during master
reset.
write operations, (selected via WCLK, WRADD and WADEN). This pin is LOW when the selected
Queue is almost-full. This flag output may be duplicated on one of the PAFn bus lines. This flag is
synchronized to WCLK.
of 8 queues (1 status word), within a selected device, having a maximum of 16 status words. During Queue
read/write operations these outputs provide programmable full flag status, in either direct or polled mode.
The mode of flag operation is determined during master reset via the state of the FM input. This flag bus
is capable of High-Impedance state, this is important during expansion of multi-queue devices. During direct
operation the PAFn bus is updated to show the PAF status of a status word of queues within a selected
device. Selection is made using WCLK, FSTR, WRADD and WADEN. During Polled operation the PAFn
bus is loaded with the PAF status of multi-queue flow-control status words sequentially based on the rising
edge of WCLK.
providing both a Packet Ready (PR) output and a Programmable Almost Empty (PAE) discrete output,
or standard mode, providing a (PAE) output only. If this pin is HIGH during Master Reset the part will
operate in packet mode, if it is LOW then almost empty mode. If packet mode has been selected the read
port flag bus becomes packet ready flag bus, PRn and the discrete packet ready flag, PR is functional.
If almost empty operation has been selected then the flag bus provides almost empty status, PAEn and
the discrete almost empty flag, PAE is functional, the PR flag is inactive and should not be connected.
Packet Ready utilizes user marked locations to identify start and end of packets being written into the device.
12
Description
DDQ
). If LVTTL I/O are required then it should be tied LOW.
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 10, 2009