IDT72T6360L6BB IDT, Integrated Device Technology Inc, IDT72T6360L6BB Datasheet - Page 22

• Manufacturer Part Number: IDT72T6360L6BB
• Description: IC FLOW-CTRL 36BIT 6NS 324-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72T6360L6BB

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72T6360L6BB

TABLE 10 – DEVICE CONFIGURATION
TABLE 12– NUMBER OF BITS REQUIRED FOR OFFSET REGISTERS
TABLE 11– DEFAULT PROGRAMMABLE
FLAG OFFSETS
IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE
x9, x18, x36 BIT WIDE CONFIGURATION
Signal Pins Static State
MTYPE[1:0]
Write Port Bus-Width
Configuration 1 (128Mb)
Configuration 1 (256Mb)
Configuration 2 (256Mb)
Configuration 3 (256Mb)
Configuration 3 (512Mb)
Configuration 4 (256Mb)
Configuration 4 (512Mb)
Configuration 5 (512Mb)
Configuration 6 (768Mb)
Configuration 7 (1Gb)
FSEL[1:0]
MSPEED
MIC[2:0]
BM[3:0]
ASYW
IOSEL
ASYR
FWFT
IDEM
JSEL
FSEL1
0
0
1
1
—
00
01
10
11
—
00
01
10
11
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Read port configured in asynchronous mode
Read port configured in synchronous mode
Write port configured in asynchronous mode
Write port configured in synchronous mode
See Table 13 - Bus-Matching Configurations
Programmable flag register offset value = 127
Programmable flag register offset value = 1,023
Programmable flag register offset value = 4,095
Programmable flag register offset value = 16,383
IDT Standard mode
FWFT mode
Depth expansion in FWFT mode
Depth expansion in IDT Standard mode
I/O voltage set to 3.3V levels
I/O voltage set to 2.5V levels
JTAG function is disabled
JTAG function is enabled
See Table 8 - MIC[2:0] Configurations for description
External memory interface clocks set to 133MHz
External memory interface clocks set to 166MHz
External memory configuration is: 4M x 32
Not used
External memory configuration is: 8M x 32
External memory configuration is: 16M x 16
EDC On
21
22
22
22
23
22
23
23
24
24
FSEL0
0
1
0
1
Configuration
x48
EDC Off
Offset n,m
22
23
23
23
24
22
23
24
24
25
16,383
1,023
4,095
127
EDC On
22
22
23
23
23
24
23
24
24
25
25
FUNCTIONAL DESCRIPTIONS
MASTER RESET AND DEVICE CONFIGURATION
determined, this includes the following:
of the above modes are selected. A master reset comprises of pulsing the MRS
input pin from high to low for a period of time (t
held in their respective states. Table 10 summarizes the configuration modes
available during master reset. These signals are described in detail in the signal
description section.
PROGRAMMABLE ALMOST EMPTY/ALMOST FULL FLAGS
an early indicator for the empty and full boundary conditions. These flags have
an offset value (n, m) that will determine the almost empty and almost full boundary
conditions. There are four default offset values selectable during master reset,
these values are shown in Table 11, Default Programmable Flag Offsets.
(SCLK, SI, and SWEN). The SFC has two internal offset registers that are used
to store the specific offset value, one for the PAE and one for the PAF. The total
number of bits (shown in Table 12, Number of Bits Required for Offset Registers)
must be completely programmed to the offset registers. The serial programming
sequence begins by writing data into the PAE register followed by the PAF
register. See Figure 29, Serial Loading of Programmable Flag Registers for
the associated timing diagram. The total number of bits required to program the
offset registers will vary depending on the type of configuration that is shown in
Figure 2a-2g, the bus-width selected, and whether EDC is used.
there are at least one to n words written in the device. Similarly PAF will become
active (LOW) when there are at least D – M words or more in the device, where
D is the density of the SFC.
During master reset the sequential flow-control configuration and settings are
1. Synchronous or Asynchronous read and write port operation
2. Bus-width configuration
3. Default offset register values
4. IDT standard or first word fall through (FWFT) timing mode
5. Depth expansion in IDT standard or FWFT mode
6. I/O voltage set to 2.5V or 3.3V levels
7. JTAG function enabled or disabled
8. Configuration of the external memory interface
The SFC has a set of programmable flags (PAE/PAF) that can be used as
Offset values can also be programmed using the serial programming pins
The values of n, m are used such that the PAE will become active (LOW) when
The state of the configuration inputs during master reset will determine which
x24
EDC Off
23
24
24
24
25
23
24
25
25
26
COMMERCIAL AND INDUSTRIAL
EDC On
23
24
24
24
25
24
25
25
26
26
RS
TEMPERATURE RANGES
) with the configuration inputs
FEBRUARY 10, 2009
x12
EDC Off
24
25
25
25
26
24
25
26
26
27