KS8695X Micrel Inc, KS8695X Datasheet - Page 18

• Manufacturer Part Number: KS8695X
• Description: IC SWITCH 10/100 5PORT 208PQFP
• Manufacturer: Micrel Inc

Specifications of KS8695X

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 208-MQFP, 208-PQFP
• For Use With: KS8695-EVAL - EVAL KIT EXPERIMENTAL KS8695576-1005 - BOARD EVAL EXPERIMENT KS8695X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

KS8695X
Signal Descriptions by Group
Clock and Reset Pins
JTAG Interface Pins
WAN Ethernet Physical Interface Pins
Note:
1. I = Input.
M9999-102604
I/O = Bidirectional.
O = Output.
O/I = Output in normal mode; input pin during reset.
150
151
148
110
111
112
113
114
159
160
162
163
158
Pin
Pin
Pin
96
83
85
CPUCLKSEL
WANFXSD/
WRSTPLS
WANRXM
WANRXP
WANTXM
WANTXP
RESETN
EROEN/
CPUCLK
URTSN/
WRSTO
XCLK1/
TRSTN
XCLK2
Name
Name
Name
DOUT
TMS
TDO
TCK
TDI
I/O Type
I/O Type
I/O Type
O/I
O/I
I/O
O
O
O
O
I
I
I
I
I
I
I
I
I
(1)
(1)
(1)
Description
External Clock In. This signal is used as the source clock for the transmit clock of the
internal MAC and PHY. The clock frequency should be 25MHz ±50ppm. The XCLK1
signal is also used as the reference clock signal for the internal PLL to generate the
125MHz internal system clock.
CPUCLK: factory clock test input when the internal PLL is disabled (factory test signal).
External Clock In. Used with XCLK1 pin when another polarity of crystal is needed.
This is unused for a normal clock input.
Normal Mode: UART request to send. Active low output.
During reset: CPU clock select. Select CPU clock source. CPUCLKSEL=0 (normal
mode), the internal PLL clock output is used as the CPU clock source.
CPUCLKSEL=1 (factory test signal): the external clock to the CPUCLK pin is used as
the internal CPU clock source.
KS8695X chip reset. Active low input asserted for at least 256 system clock (40ns)
cycles to reset the KS8695X. When in the reset state, all the output pins are tri-stated
and all open drain signals are floating.
Watchdog timer reset output. This signal is asserted for at least 200ms if
RESETN is asserted or when the internal watchdog timer expires.
Normal Mode: ROM/SRAM/FLASH and External I/O output enable. Active low. When
asserted, this signal controls the output enable port of the specified device.
During reset: Watchdog timer reset polarity setting. WRSTPLS=0, Active high;
WRSTPLS=1, Active low. No default.
Description
JTAG test clock.
JTAG test mode select.
JTAG test data in.
JTAG test data out.
JTAG test reset. Active low.
Description
WAN PHY receive signal + (differential).
WAN PHY receive signal – (differential).
WAN PHY transmit signal – (differential).
WAN PHY transmit signal + (differential).
WAN fiber signal detect. Signal detect input when the WAN port is operated in
100BASE-FX 100Mb fiber mode. DOUT: factory analog test mode.
18
October 2004
Micrel