CDB5368 Cirrus Logic Inc, CDB5368 Datasheet
CDB5368
Specifications of CDB5368
Related parts for CDB5368
CDB5368 Summary of contents
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A/D Converter Features Advanced Multi-bit Delta-Sigma Architecture 24-Bit Conversion 114 dB Dynamic Range -105 dB THD+N Supports Audio Sample Rates up to 216 kHz Selectable Audio Interface Formats – ...
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... The CS5368 is available in a 48-pin LQFP (-40°C to +105°C). The CDB5368 Customer Demonstration board is also available for device evaluation and implementation suggestions. Please see The CS5368 is ideal for high-end and pro-audio systems requiring unrivaled sound quality, transparent conversion, wide dynamic range and negligible distortion, such as A/V receivers, digital mixing consoles, multi-channel record- ers, outboard converters, digital effect processors, and automotive audio systems ...
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TABLE OF CONTENTS 1. PIN DESCRIPTION ................................................................................................................................. 6 2. TYPICAL CONNECTION DIAGRAM 3. CHARACTERISTICS AND SPECIFICATIONS .................................................................................... 10 RECOMMENDED OPERATING CONDITIONS ................................................................................. 10 ABSOLUTE RATINGS ....................................................................................................................... 10 SYSTEM CLOCKING ......................................................................................................................... 10 DC POWER ........................................................................................................................................ 11 LOGIC LEVELS ................................................................................................................................. 11 PSRR, ...
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Global Mode Control Register ................................................................................... 32 5.4 02h (OVFL) Overflow Status Register ........................................................................................... 33 5.5 03h (OVFM) Overflow Mask Register ............................................................................................ 33 5.6 04h (HPF) High-Pass Filter Register ............................................................................................. 34 5.7 05h Reserved ................................................................................................................................ 34 5.8 06h ...
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LIST OF TABLES Table 1. Power Supply Pin Definitions ...................................................................................................... 19 Table 2. DIF1 and DIF0 Pin Settings ........................................................................................................ 23 Table 3. M1 and M0 Settings .................................................................................................................... 23 Table 4. Frequencies for 48 kHz Sample Rate using LJ/I²S ..................................................................... 25 ...
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PIN DESCRIPTION AIN2+ 1 AIN2- 2 GND REF_GND 5 FILT GND GND 11 AIN4+ 12 AIN4- 13 ...
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Pin Name Pin # AIN2+, AIN2- 1,2 AIN4+, AIN4- 11,12 AIN3+, AIN3- 13,14 AIN7+, AIN7- 15,16 Differential Analog (Inputs) - Audio signals are presented differently to the delta sigma modula- AIN8+, AIN8- 17,18 tors via the AIN+/- pins. AIN6+, AIN6- ...
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Control Port Mode CLKMODE (Input) - This pin is ignored in Control Port Mode and the same functionality is CLKMODE 34 obtained from the corresponding bit in the Global Control Register. Note: Should be connected to GND when using the ...
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TYPICAL CONNECTION DIAGRAM Resistor may only be used derived from VA. If used, do not drive any other logic from VD. + μ F 0.01 μ FILT+ + 220 μ F 0.1 ...
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CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS GND = 0 V, all voltages with respect Parameter DC Power Supplies: Ambient Operating Temperature 1. TDM Quad-Speed Mode specified to operate correctly at VLS ≥ 3.14 V. ABSOLUTE RATINGS ...
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DC POWER MCLK = 12.288 MHz; Master Mode; GND = 0 V. Parameter Power Supply Current (Normal Operation) Power Supply Current (Power-Down) (Note 1) Power Consumption Normal Operation VLS = VLC = ...
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ANALOG CHARACTERISTICS (COMMERCIAL) Test Conditions (unless otherwise specified VLS = VLC 3.3 V, and T sine wave. Measurement Bandwidth kHz. Parameter Single-Speed Mode kHz Dynamic Range ...
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ANALOG CHARACTERISTICS (AUTOMOTIVE) Test Conditions (unless otherwise specified 5. 5.25 to 3.14 V, VLS = VLC = 5.25 to 1.71 V and T = -40° to +85° C. Full-scale input sine wave. Measurement ...
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DIGITAL FILTER CHARACTERISTICS Parameter Single-Speed Mode (2 kHz to 54 kHz sample rates) Passband (Note 1) Passband Ripple Stopband (Note 1) Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) Double-Speed Mode (54 kHz to 108 kHz sample rates) ...
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SERIAL AUDIO INTERFACE - I²S/LJ TIMING The serial audio port is a three-pin interface consisting of SCLK, LRCK and SDOUT. Logic "0" = GND = 0 V; Logic "1" = VLS; C Parameter Sample Rates Master Mode SCLK Frequency SCLK ...
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SERIAL AUDIO INTERFACE - TDM TIMING The serial audio port is a three-pin interface consisting of SCLK, LRCK and SDOUT. Logic "0" = GND = 0 V; Logic "1" = VLS; C Parameter Sample Rates Master Mode SCLK Frequency SCLK ...
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SWITCHING SPECIFICATIONS - CONTROL PORT - I²C TIMING Inputs: Logic 0 = DGND, Logic 1 = VLC, SDA C Parameter SCL Clock Frequency RST Rising Edge to Start Bus Free Time Between Transmissions Start Condition Hold Time (prior to first ...
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SWITCHING SPECIFICATIONS - CONTROL PORT - SPI TIMING Inputs: Logic 0 = DGND, Logic 1 = VLC, CDOUT C Parameter CCLK Clock Frequency RST Rising Edge to CS Falling CS Falling to CCLK Edge CS High Time Between Transmissions CCLK ...
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... Clocks should be kept away from the FILT+ and VQ pins in order to avoid unwanted coupling of these signals into the device. The FILT+ and VQ decoupling capac- itors must be positioned to minimize the electrical path to ground. The CDB5368 evaluation board demonstrates optimum layout for the device. 4.2 Control Port Mode and Stand-Alone Operation 4 ...
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Master Clock Source The CS5368 requires a Master Clock that can come from one of two sources: an on-chip crystal oscillator driver or an externally generated clock. 4.3.1 On-Chip Crystal Oscillator Driver When using the on-board crystal oscillator driver, ...
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Master and Slave Operation CS5368 operation depends on two clocks that are synchronously derived from MCLK: SCLK and LRCK/FS. See Section 4.5 on page 22 The CS5368 can operate as either clock master or clock slave with respect to ...
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Serial Audio Interface (SAI) Format The SAI port consists of two timing pins (SCLK, LRCK/FS) and four audio data output pins (SDOUT1/TDM, SDOUT2, SDOUT3/TDM and SDOUT4). The CS5368 output is serial data in I²S, Left-Justified (LJ), or Time Division ...
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TDM Format In TDM Mode, all eight channels of audio data are serially clocked out during a single Frame Sync (FS) cycle, as shown in Figure channel slot occupies 32 SCLK cycles, with the data left justified and with ...
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Master Mode Clock Dividers Figure 13 shows the configuration of the MCLK dividers and the sample rate dividers for Master Mode, in- cluding the significance of each MCLK divider pin (in Stand-Alone Mode) or bit (in Control Port Mode). ...
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Master and Slave Clock Frequencies Tables 4 through 12 show the clock speeds for sample rates of 48 kHz, 96 kHz and 192 kHz. The MCLK/LRCK ratio should be kept at a constant value during each mode. In Master ...
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TDM MASTER MCLK Divider MCLK (MHz) SCLK (MHz) MCLK/FS Ratio SCLK/FS Ratio Table 9. Frequencies for 96 kHz Sample Rate using TDM TDM SLAVE MCLK Divider MCLK (MHz) SCLK (MHz) MCLK/FS Ratio SCLK/FS Ratio Table 10. Frequencies for 96 kHz ...
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Reset The device should be held in reset until power is applied and all incoming clocks are stable and valid. Upon de-assertion of RST, the state of the configuration pins is latched, the state machine begins, and the device ...
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Analog Connections The analog modulator samples the input at half of the internal Master Clock frequency, or 6.144 MHz nom- inally. The digital filter will reject signals within the stopband of the filter. However, there is no rejection of ...
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Optimizing Performance in TDM Mode Noise Management is a design technique that is utilized in the majority of audio A/D converters. Noise man- agement is relatively simple conceptually. The goal of noise management is to interleave the on-chip digital ...
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Control Port Operation The Control Port is used to read and write the internal device registers. It supports two industry standard formats, I²C and SPI. The part is in I²C format by default. SPI Mode is selected if there ...
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I²C Mode In I²C Mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL. There pin. Pins AD0 and AD1 form the two least-significant bits of ...
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REGISTER MAP In Control Port Mode, the bits in these registers are used to control all of the programmable features of the ADC. All registers above 0Ah are RESERVED. 5.1 Register Quick Reference Adr Name 7 00 REVI 01 ...
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Bits[5:4] MDIV[1:0] Each bit selects an XTI divider. When either bit is low, an XTI divide-by-1 function is selected. When either bit is HIGH, an XTI divide-by-2 function is selected. With both bits HIGH, XTI is divid ...
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High-Pass Filter Register R R/W HPF8 HPF7 Default: 0x00, all high-pass filters enabled. The High-Pass Filter Register is used to enable or disable a high-pass filter that exists for each channel. These filters are used ...
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Reserved R RESERVED - - 5.12 0Ah (SDEN) SDOUT Enable Control Register R R/W RESERVED Default: 0x00, all SDOUT pins enabled. The SDOUT Enable Control Register is used to tri-state the serial audio data ...
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FILTER PLOTS 0.1 0.08 0.06 0.04 0.02 0 −0.02 −0.04 −0.06 −0.08 −0.1 0 0.05 0.1 0.1 0.08 0.06 0.04 0.02 0 −0.02 −0.04 −0.06 −0.08 −0.1 0 0.05 0.1 0.1 0.08 0.06 0.04 0.02 0 −0.02 −0.04 −0.06 ...
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DS624F4 0.3 0.4 0.5 0.6 Frequency (normalized to ...
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0 −0.2 −0.4 −0.6 −0.8 −1 −1.2 −1.4 −1.6 −1.8 −2 0.4 0.42 0.44 0 −0.2 −0.4 −0.6 −0.8 −1 −1.2 −1.4 −1.6 −1.8 −2 0.4 0.42 0.44 0 −0.2 −0.4 −0.6 −0.8 −1 −1.2 −1.4 −1.6 −1.8 −2 0.2 ...
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PARAMETER DEFINITIONS Dynamic Range The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made with ...
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PACKAGE DIMENSIONS 48L LQFP PACKAGE DRAWING D D DIM MIN A --- A1 0.002 B 0.007 D 0.343 D1 0.272 E 0.343 E1 0.272 e* 0.016 L 0.018 ∝ 0.000° * Nominal pin pitch is 0.50 mm Controlling dimension ...
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... CS5368 8-channel A/D LQFP Converter CDB5368 Evaluation Board for CS5368 10.REVISION HISTORY Revision Updated the wording of pin 24, LRCK/FS, in the pin description table on page 7 to correctly reflect the F2 high/low clocking state for odd-channel selection in I²S and LJ Modes. ...
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Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one nearest you IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this ...