CDB5368 Cirrus Logic Inc, CDB5368 Datasheet - Page 27

• Manufacturer Part Number: CDB5368
• Description: BOARD EVAL FOR CS5368 192KHZ ADC
• Manufacturer: Cirrus Logic Inc

Specifications of CDB5368

• Number Of Adc's: 1
• Number Of Bits: 24
• Sampling Rate (per Second): 192k
• Data Interface: Serial
• Inputs Per Adc: 8 Differential
• Input Range: ±0.3 V
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: CS5368
• Description/function: Audio A/D
• Operating Supply Voltage: 3.3 V
• Product: Audio Modules
• For Use With/related Products: CS5368
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1157

DS624F4
4.8
4.8.1 Power-Down Mode
4.9
4.9.1 Overflow in Stand-Alone Mode
4.9.2 Overflow in Control Port Mode
Reset
The device should be held in reset until power is applied and all incoming clocks are stable and valid. Upon
de-assertion of RST, the state of the configuration pins is latched, the state machine begins, and the device
starts sending audio output data a maximum of 524288 MCLK cycles after the release of RST. When chang-
ing between mode configurations in Stand-Alone Mode, including clock dividers, serial audio interface for-
mat, master/slave, or speed modes, it is recommended to reset the device following the change by holding
the RST pin low for a minimum of one MCLK cycle and then restoring the pin to a logic-high condition.
Overflow Detection
The CS5368 features a Power-Down Mode in which power is temporarily withheld from the modulators, the
crystal oscillator driver, the digital core, and the serial port. The user can access Power-Down Mode by
holding the device in reset and holding all clock lines at a static, valid logic level (either logic-high or logic-
low).
The CS5368 includes overflow detection on all input channels. In Stand-Alone Mode, this information is
presented as open drain, active low on the OVFL pin. The pin will go to a logical low as soon as an over-
range condition in any channel is detected. The data will remain low, then time-out as specified in
"Overflow Timeout" on page
been any other over-range condition detected. Note that an over-range condition on any channel will restart
the time-out period.
In Control Port Mode, the Overflow Status Register interacts with the Overflow Mask Register to provide
interrupt capability for each individual channel. See
page 33
“DC Power” on page 11
for details on these two registers.
14. After the time-out, the OVFL pin will return to a logical high if there has not
shows the power-saving associated with Power-Down Mode.
Section 5.4 "02h (OVFL) Overflow Status Register" on
CS5368
Section
27