KDC5514-Q48EVAL Intersil, KDC5514-Q48EVAL Datasheet - Page 28

• Manufacturer Part Number: KDC5514-Q48EVAL
• Description: DAUGHTER CARD FOR KAD5514
• Manufacturer: Intersil
• Series: FemtoCharge™r

Specifications of KDC5514-Q48EVAL

• Number Of Adc's: 1
• Number Of Bits: 14
• Sampling Rate (per Second): 250M
• Data Interface: Parallel
• Inputs Per Adc: 1 Differential
• Input Range: 1.47 Vpp
• Power (typ) @ Conditions: 429mW @ 250MSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: KAD5514P-25, KMB001 Motherboard
• For Use With: KMB001LEVAL - MOTHERBOARD FOR LVDS ADC CARD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NOTE:
13. At power-up, the DDR Enable bit is at a logic ‘0’ for the 72 pin package and set to a logic ‘1’ internally for the 48 pin package by an internal pull-up..
76-BF
C6-FF
60-6F
(Hex)
Addr
C0
C1
C2
C3
C4
C5
70
71
72
73
74
75
output_mode_A
output_mode_B
user_patt1_msb
user_patt2_msb
user_patt1_lsb
user_patt2_lsb
config_status
clock_divide
Parameter
phase_slip
Reserved
reserved
reserved
reserved
reserved
test_io
Name
User Test Mode [1:0]
(MSB)
28
Bit 7
B15
B15
B7
B7
10 = Reserved
11 = Reserved
01 = Alternate
00 = Single
other codes = reserved
Output Mode [2:0]
000 = Pin Control
001 = LVDS 2mA
010 = LVDS 3mA
100 = LVCMOS
DLL Range
1 = slow
0 = fast
Result
Bit 6
XOR
B14
B14
B6
B6
TABLE 16. SPI MEMORY MAP (Continued)
Bit 5
B13
B13
B5
B5
KAD5514P
Reserved
(Note 13)
Enable
Result
Bit 4
DDR
XOR
B12
B12
B4
B4
Reserved
Reserved
Reserved
Reserved
Reserved
1 = Midscale Short
4 = Checker Board
2 = +FS Short
3 = -FS Short
Bit 3
5 = reserved
6 = reserved
B11
B11
B3
B3
0 = Off
Output Test Mode [3:0]
Bit 2
B10
B10
001 = Twos Complement
B2
B2
other codes = reserved
other codes = reserved
Output Format [2:0]
100 = Offset Binary
Clock Divide [2:0]
000 = Pin Control
000 = Pin Control
010 = Gray Code
001 = divide by 1
010 = divide by 2
100 = divide by 4
7 = One/Zero Word
Bit 1
9-15 = reserved
B1
B9
B1
B9
8 = User Input
Toggle
(LSB)
Clock
Edge
Bit 0
Next
B0
B8
B0
B8
affected by
affected by
affected by
Def. Value
Read Only
Soft Reset
Soft Reset
Soft Reset
(Hex)
NOT
NOT
NOT
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
September 10, 2009
Indexed/
Global
FN6804.2
G
G
G
G
G
G
G
G
G
G
G