AD9216-105PCBZ Analog Devices Inc, AD9216-105PCBZ Datasheet - Page 23

• Manufacturer Part Number: AD9216-105PCBZ
• Description: BOARD EVAL FOR AD9216 105MSPS
• Manufacturer: Analog Devices Inc

Specifications of AD9216-105PCBZ

• Number Of Adc's: 2
• Number Of Bits: 10
• Sampling Rate (per Second): 105M
• Data Interface: Parallel
• Inputs Per Adc: 2 Differential
• Input Range: 2 Vpp
• Power (typ) @ Conditions: 300mW @ 105MSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9216-105
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

OUTPUT CODING
Table 8.
Code
1023
1023
1022
513
512
511
1
0
0
TIMING
The AD9216 provides latched data outputs with a pipeline delay
of six clock cycles. Data outputs are available one propagation
delay (t
Figure 2 for a detailed timing diagram.
The length of the output data lines and loads placed on them
should be minimized to reduce transients within the AD9216.
These transients can detract from the converter’s dynamic
performance. The lowest conversion rate of the AD9216 is
10 MSPS. At clock rates below 10 MSPS, dynamic perform-
ance may degrade.
•
•
•
•
PD
(VIN+) − (VIN−)
> +0.998 V
+0.998 V
+0.996 V
+0.002 V
+0.0 V
−0.002 V
−0.998 V
−1.000 V
< −1.000 V
) after the rising edge of the clock signal. Refer to
A
B
Figure 46. Example of Multiplexed Data Format Using the Channel A Output and the Same Clock Tied to CLK_A, CLK_B, and MUX_SELECT
–1
–1
•
•
•
•
B
–7
A
B
0
0
A
–6
Offset Binary
11 1111 1111
11 1111 1111
11 1111 1110
10 0000 0001
10 0000 0000
01 1111 1111
00 0000 0001
00 0000 0000
00 0000 0000
B
–6
A
B
1
1
•
•
•
•
A
–5
B
–5
A
B
2
2
Twos Complement
01 1111 1111
01 1111 1111
01 1111 1110
00 0000 0001
00 0000 0000
11 1111 1111
10 0000 0001
10 0000 0000
10 0000 0000
A
–4
B
–4
A
B
•
•
•
•
3
3
A
–3
Rev. A | Page 23 of 40
B
–3
A
B
4
4
A
–2
B
–2
DATA FORMAT
The AD9216 data output format can be configured for either
twos complement or offset binary. This is controlled by the
data format select pin (DFS). Connecting DFS to AGND
produces offset binary output data. Conversely, connecting
DFS to AVDD formats the output data as twos complement.
The output data from the dual ADCs can be multiplexed onto a
single, 10-bit output bus. The multiplexing is accomplished by
toggling the MUX_SELECT bit, which directs channel data to
the same or opposite channel data port. When MUX_SELECT
is logic high, the Channel A data is directed to the Channel A
output bus, and the Channel B data is directed to the Channel B
output bus. When MUX_SELECT is logic low, the channel
data is reversed; that is, the Channel A data is directed to the
Channel B output bus, and the Channel B data is directed to
the Channel A output bus. By toggling the MUX_SELECT bit,
multiplexed data is available on either of the output data ports.
If the ADCs are run with synchronized timing, this same clock
can be applied to the MUX_SELECT pin. Any skew between
CLK_A, CLK_B, and MUX_SELECT can degrade ac perform-
ance. It is recommended to keep the clock skew < 100 pHs.
After the MUX_SELECT rising edge, either data port has
the data for its respective channel; after the falling edge, the
alternate channel’s data is placed on the bus. Typically, the
other unused bus is disabled by setting the appropriate OEB
high to reduce power consumption and noise. Figure 46 shows
an example of multiplex mode. When multiplexing data, the
data rate is two times the sample rate. Note that both channels
must remain active in this mode and that each channel’s power-
down pin must remain low.
A
B
5
5
A
–1
B
–1
A
B
6
6
A
0
B
0
A
B
7
7
A
1
B
1
A
B
8
8
ANALOG INPUT
ADC A
ANALOG INPUT
ADC B
CLK_A = CLK_B =
MUX_SELECT
D0_A
–D11_A
AD9216