AD9216-105PCBZ Analog Devices Inc, AD9216-105PCBZ Datasheet - Page 26

• Manufacturer Part Number: AD9216-105PCBZ
• Description: BOARD EVAL FOR AD9216 105MSPS
• Manufacturer: Analog Devices Inc

Specifications of AD9216-105PCBZ

• Number Of Adc's: 2
• Number Of Bits: 10
• Sampling Rate (per Second): 105M
• Data Interface: Parallel
• Inputs Per Adc: 2 Differential
• Input Range: 2 Vpp
• Power (typ) @ Conditions: 300mW @ 105MSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9216-105
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9216
DUAL ADC LFCSP PCB
The PCB requires a low jitter clock source, analog sources,
and power supplies. The PCB interfaces directly with ADI’s
standard dual-channel data capture board (HSC-ADC-EVAL-
DC), which together with ADI’s ADC Analyzer™ software
allows for quick ADC evaluation.
POWER CONNECTOR
Power is supplied to the board via three detachable
4-lead power strips.
Table 10. Power Connector
Terminal
VCC
VDD
VDL
VCLK 3.0 V
+5 V
−5 V
1
ANALOG INPUTS
The evaluation board accepts a 2 V p-p analog input signal
centered at ground at two SMB connectors, Input A and
Input B. These signals are terminated at their respective
primary side transformer. T1 and T2 are wideband RF
transformers that provide the single-ended-to-differential
conversion, allowing the ADC to be driven differentially,
minimizing even-order harmonics. The analog signals can
be low-pass filtered at the secondary transformer to reduce
high frequency aliasing.
OPTIONAL OPERATIONAL AMPLIFIER
The PCB has been designed to accommodate an optional
AD8139 op amp that can serve as a convenient solution
for dc-coupled applications. To use the AD8139 op amp,
remove C14, R4, R5, C13, R37, and R36, and place R22, R23,
R30, and R24.
VCC, VDD, and VDL are the minimum required power connections.
1
1
1
3.0 V
2.5 V
2.5 V
Comments
Analog supply for ADC
Output supply for ADC
Buffer supply
Supply for XOR Gates
Optional op amp supply
Optional op amp supply
Rev. A | Page 26 of 40
CLOCK
The single-clock input is at J5; the input clock is buffered and
drives both channel input clocks from Pin 3 at U8 through R79,
R40, and R85. Jumper E11 to E19 allows for inverting the input
clock. U8 also provides CLKA and CLKB outputs, which are
buffered by U6 and U5, which drive the DRA and DRB signals
(these are the data-ready clocks going off card). DRA and DRB
can also be inverted at their respective jumpers.
Table 11. Jumpers
Terminal
OEB A
PWDN A
MUX
SHARED REF
DRA
LATA
ENC A
OEB B
PWDN B
DFS
SHARED REF
DRB
LATB
ENC B
VOLTAGE REFERENCE
The ADC SENSE pin is brought out to E41, and the internal
reference mode is selected by placing a jumper from E41 to
ground (E27). External reference mode is selected by placing a
jumper from E41 to E25 and E30 to E2. R56 and R45 allow for
programmable reference mode selection.
DATA OUTPUTS
The ADC outputs are buffered on the PCB at U2, U4. The ADC
outputs have the recommended series resistors in line to limit
switching transient effects on ADC performance.
Shared Reference Input
Invert A Latch Clock
Shared Reference Input
Invert B Latch Clock
Comments
Output Enable for A Side
Power-Down A
Mux Input
Invert DRA
Invert Encode A
Output Enable for B Side
Power-Down B
Data Format Select
Invert DRB
Invert Encode B