CDB5381 Cirrus Logic Inc, CDB5381 Datasheet - Page 4

• Manufacturer Part Number: CDB5381
• Description: BOARD EVAL FOR CS5381 192KHZ ADC
• Manufacturer: Cirrus Logic Inc

Specifications of CDB5381

• Number Of Adc's: 2
• Number Of Bits: 24
• Sampling Rate (per Second): 192k
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 6.1 Vpp
• Power (typ) @ Conditions: 360mW @ 5 V
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -10°C ~ 70°C
• Utilized Ic / Part: CS5381
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1008

4
J7
J8
J13
S1
S2
* denotes default factory settings
-12 V
+12 V
VD
VL
GND
+5 V
AINL
AINR
Optical Output
Coax Output
JUMPER/SWITCH
CONNECTOR
VD Power Source
VL Power Source
Input/Output for
clocks/data
Reset for the CDB5381
CDB5381 Configuration
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
INPUT/OUTPUT
PURPOSE
Table 2. CDB5381 Jumper and Switch Settings
Table 1. System Connections
-12 V power for the input op-amps
+12 V power for the input op-amps
+3.3 V to +5 V power for the CS5381
+2.5 V to +5 V power for the CS5381
Ground connection from power supply
+ 5 Volt power
Differential analog input left channel
Differential analog input right channel
Digital audio output
Digital audio output
ADJ
*+3.3 V
+5 V
ADJ
*+3.3 V
+5 V
-
-
M1/M0
ADC
HPF
DIV
IO_HDR
DIF
8406
POSITION
Open
*Closed
*Open
Closed
Open
*Closed
Open
*Closed
Open
*Closed
Open
*Closed
Open
*Closed
SIGNAL PRESENT
Power from the Binding Post (J3)
Power from the +3.3 V Regulator
Power from the +5V Supply
Power from the Binding Post (J4)
Power from the +3.3 V Regulator
Power from the +5 V Supply
-
-
Hi
Low
CS5381 in Master mode
CS5381 in Slave mode
High-pass filter is disabled
High-pass filter is enabled
MCLK is divided by two internally by the
CS5381
MCLK is not divided internally by the
CS5381
Header J3 is an input for clocks
Header J3 is an output for clocks and
data
Digital interface format set to I
Digital interface format set to Left Justi-
fied
CS8406 in Master mode
CS8406 in Slave mode
FUNCTION SELECTED
CDB5381
DS563DB1
2
S