ADC121S625EVAL/NOPB National Semiconductor, ADC121S625EVAL/NOPB Datasheet - Page 16

• Manufacturer Part Number: ADC121S625EVAL/NOPB
• Description: BOARD EVALUATION FOR ADC121S625
• Manufacturer: National Semiconductor

Specifications of ADC121S625EVAL/NOPB

• Number Of Adc's: 1
• Number Of Bits: 12
• Sampling Rate (per Second): 200k
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: ±VREF
• Power (typ) @ Conditions: 2.25mW @ 200kSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC121S625
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC121S625EVAL

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Functional Description
3.0 SERIAL DIGITAL INTERFACE
The ADC121S625 communicates via a synchronous 3-wire
serial interface as shown in the timing diagram. Each output
bit is sent on the falling edge of SCLK. While most receiving
systems will capture the digital output bits on the rising edge
of SCLK, the falling edge of SCLK may be used to capture
each bit if the minimum hold time for D
Differential
Single-Ended
FIGURE 1. V
Input Signal
FIGURE 2. V
TABLE 1. Allowable V
CM
CM
range for Differential Input operation
V
range for single-ended operation
Minimum V
REF
V
REF
/ 2 − 0.3V
− 0.3V
CM
CM
OUT
Range
Maximum V
(Continued)
− ( V
V
V
is acceptable.
A
A
− V
REF
+ 0.3V
+ 0.3V
20132762
REF
20132761
/ 2 )
CM
16
3.1 Digital Inputs
The Digital inputs consist of the SCLK and CS. A falling CS
initiates the conversion and data transfer. The time between
the fall of CS and the second falling edge of SCLK is used to
sample the input signal. The data output is enabled at the
second falling edge of SCLK that follows the fall of CS. Since
the first bit clocked out is a null bit, the MSB is clocked out on
the third falling edge of SCLK after the fall of CS. For the
next 12 SCLK periods D
most significant bit first. After the least significant bit (B0) has
been output, the output data is repeated if CS remains low
after the LSB is output, but in a least significant bit first
format, with the LSB being output only once, as indicated in
the Double Cycle Timing Diagram. D
impedance state after the B9 - B10 - B11 sequence. If CS is
raised between prior to or at the 15th clock fall, D
into its high impedance state after the LSB (B0) is output and
the data is not repeated. Additional clock cycles will not
effect the converter. A new conversion is initiated only when
CS has been taken HIGH and returned LOW.
3.1 SCLK Input
The SCLK (serial clock) is used to time the conversion
process and to clock out the conversion results. This input is
TTL/CMOS compatible. Internal settling time limits the maxi-
mum clock frequency and internal capacitor leakage, or
droop,
ADC121S625 offers guaranteed performance with clock
rates in the range indicated in the electrical table.
3.2 Data Output
The output data format of the ADC121S625 is Two’s
Complement, as shown in Table 2. This table indicates the
ideal output code for the given input voltage and does not
include the effects of offset, gain error, linearity errors, or
noise.
Applications Information
OPERATING CONDITIONS
We recommend that the following conditions be observed for
operation of the ADC121S625:
−40˚C ≤ T
+4.5V V
0.1V ≤ V
0.8 MHz ≤ f
V
+ Full Scale
Midscale
Midscale
− 1 LSB
− Full Scale
CM
Description
: See Section 2.3
TABLE 2. Ideal Output Code vs. Input Voltage
A
REF
limits
≤ +5.5V
A
CLK
≤ +85˚C
≤ 2.5V
Analog Input
≤ 4.8 MHz
(+IN) − (−IN)
the
0V − 1 LSB
− 1 LSB
−V
V
0V
REF
REF
minimum
OUT
will output the conversion result,
0000 0000 0000
1000 0000 0000
0111 1111 1111
Binary Output
1111 1111 1111
Complement
clock
OUT
2’s
will go into its high
frequency.
OUT
Comp.
Code
Hex
FFF
7FF
000
800
2’s
will go
The