ADC11DV200EB/NOPB National Semiconductor, ADC11DV200EB/NOPB Datasheet - Page 19

• Manufacturer Part Number: ADC11DV200EB/NOPB
• Description: EVAL BOARD FOR ADC11DV200
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC11DV200EB/NOPB

• Number Of Adc's: 2
• Number Of Bits: 11
• Sampling Rate (per Second): 200M
• Data Interface: Parallel
• Inputs Per Adc: 1 Differential
• Input Range: 1.5 Vpp
• Power (typ) @ Conditions: 450mW @ 200MSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC11DV200
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

series inductance) 0.1 µF capacitor placed very close to the
pin to minimize stray inductance. A 0.1 µF capacitor should
be placed between V
sible. This configuration is shown in Figure 8. It is necessary
to avoid reference oscillation, which could result in reduced
SFDR and/or SNR. V
temperature stable 0.9V reference. The remaining pins
should not be loaded.
Smaller capacitor values than those specified will allow faster
recovery from the power down mode, but may result in de-
graded noise performance. Loading any of these pins, other
than V
The nominal voltages for the reference bypass pins are as
follows:
2.3 DF/DCS Pin
Duty cycle stabilization and output data format are selectable
using this quad state function pin. When enabled, duty cycle
stabilization can compensate for clock inputs with duty cycles
ranging from 30% to 70% and generate a stable internal clock,
improving the performance of the part. See Table 1 for DF/
DCS voltage vs output format description. DCS mode of op-
eration is limited to 65 MHz
3.0 DIGITAL INPUTS
Digital CMOS compatible inputs consist of CLK, PD_A,
PD_B, and OUTSEL.
3.1 Clock Input
The CLK controls the timing of the sampling process. To
achieve the optimum noise performance, the clock input
should be driven with a stable, low jitter clock signal in the
range indicated in the Electrical Table. The clock input signal
should also have a short transition region. This can be
achieved by passing a low-jitter sinusoidal clock source
V
V
V
RM
RP
RN
RM
= 1.33 V
= 0.55 V
= 0.9 V
may result in performance degradation.
RP
RM
and V
may be loaded to 1mA for use as a
≤
RN
f
CLK
as close to the pins as pos-
≤
200 MHz.
19
through a high speed buffer gate. The trace carrying the clock
signal should be as short as possible and should not cross
any other signal line, analog or digital, not even at 90°.
If the clock is interrupted, or its frequency is too low, the
charge on the internal capacitors can dissipate to the point
where the accuracy of the output data will degrade. This is
what limits the minimum sample rate.
The clock line should be terminated at its source in the char-
acteristic impedance of that line. Take care to maintain a
constant clock line impedance throughout the length of the
line. Refer to Application Note AN-905 for information on set-
ting characteristic impedance. It is highly desirable that the
the source driving the ADC clock pins only drive that pin.
The duty cycle of the clock signal can affect the performance
of the A/D Converter. Because achieving a precise duty cycle
is difficult, the ADC11DV200 has a Duty Cycle Stabilizer.
4.0 DIGITAL OUTPUTS
Digital outputs consist of the LVDS signals D0-D10 and
DRDY.
The ADC11DV200 has 12 LVDS compatible data output pins:
11 data output pins corresponding to the converted input val-
ue, and a data ready (DRDY) signal that should be used to
capture the output data. Valid data is present at these outputs
while the PD pin is low. A-Channel data should be captured
and latched with the rising edge of the DRDY signal and B-
Channel data should be captured and latched with the falling
edge of DRDY.
To minimize noise due to output switching, the load currents
at the digital outputs should be minimized. This can be
achieved by keeping the PCB traces less than 2 inches long;
longer traces are more susceptible to noise. The character-
istic impedance of the LVDS traces should be 100Ω, and the
effective capacitance < 10pF. Try to place the 100Ω termina-
tion resistor as close to the receiving circuit as possible. (See
Figure 8)
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