ADC11DV200EB/NOPB National Semiconductor, ADC11DV200EB/NOPB Datasheet - Page 5

• Manufacturer Part Number: ADC11DV200EB/NOPB
• Description: EVAL BOARD FOR ADC11DV200
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC11DV200EB/NOPB

• Number Of Adc's: 2
• Number Of Bits: 11
• Sampling Rate (per Second): 200M
• Data Interface: Parallel
• Inputs Per Adc: 1 Differential
• Input Range: 1.5 Vpp
• Power (typ) @ Conditions: 450mW @ 200MSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC11DV200
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CMOS Output Mode
ANALOG POWER
DIGITAL POWER
22, 55, 58, EP
8, 16, 18, 59,
Voltage on DF/DCS
1400mV
1, 4, 12, 15,
250 mV
750 mV
0 mV
32-35,51
47-50,52
Min
Pin No.
24-29,
39-44,
21, 54
31, 45
30, 46
37
38
60
1250 mV
600 mV
200mV
Max
V
A
DA0-DA10
DB0-DB10
Symbol
DRGND
DRDYA
DRDYB
AGND
V
V
V
DR
DF
A
D
1
0
1
0
TABLE 1. Voltage on DF/DCS Pin and Corresponding Chip Response
DCS
1
0
0
1
2's complement data, duty cycle correction on
Offset binary data, duty cycle correction off
2's complement data, duty cycle correction off
Offset binary data, duty cycle correction on
Equivalent Circuit
5
Results
Digital data output pins that make up the 11-bit conversion
result for Channel A. DA0 (pin 24) is the LSB, while DA10 (pin
51) is the MSB of the output word. Output levels are CMOS
compatible.
Digital data output pins that make up the 11-bit conversion
result for Channel B. DB0 (pin 39) is the LSB, while DB10 (pin
52) is the MSB of the output word. Output levels are CMOS
compatible.
Data Ready Strobe for channel A. This signal is used to clock
the A-Channel output data. DRDYA is a SDR clock with same
frequency as CLK rate and data is valid on the rising edges.
Data Ready Strobe for channel B. This signal is used to clock
the B-Channel output data. DRDYB is a SDR clock with same
frequency as CLK rate and data is valid on the rising edges.
Positive analog supply pins. These pins should be connected
to a quiet source and be bypassed to AGND with 0.1 µF
capacitors located close to the power pins.
The ground return for the analog supply.
Exposed Pad (EP) must be soldered to AGND to ensure rated
performance.
Positive digital supply pins. These pins should be connected
to a quiet source and be bypassed to AGND with 0.1 µF
capacitors located close to the power pins.
Positive driver supply pin for the output drivers. This pin should
be connected to a quiet voltage source and be bypassed to
DRGND with a 0.1 µF capacitor located close to the power
pin.
The ground return for the digital output driver supply. This pin
should be connected to the system digital ground.
Description
Tie to AGND
Leave floating
Tie to VA
Suggestions
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