STEVAL-ISA050V1 STMicroelectronics, STEVAL-ISA050V1 Datasheet - Page 25

• Manufacturer Part Number: STEVAL-ISA050V1
• Description: KIT EVAL PM6641 CHIPSET/DDR2/3
• Manufacturer: STMicroelectronics
• Type: DC/DC Switching Converters, Regulators & Controllersr

Specifications of STEVAL-ISA050V1

• Main Purpose: Special Purpose DC/DC, DDR Memory Supply
• Outputs And Type: 4, Non-Isolated
• Power - Output: 14.7W
• Voltage - Output: 1.05V, 1.5V, 1.8V, 0.9V
• Current - Output: 4A, 2.8A, 2.5A, 2A
• Voltage - Input: 2.7 ~ 5.5V
• Regulator Topology: Buck
• Frequency - Switching: 750kHz
• Board Type: Fully Populated
• Utilized Ic / Part: PM6641
• Input Voltage: 2.7 V to 5.5 V
• Product: Power Management Modules
• Silicon Manufacturer: ST Micro
• Silicon Core Number: PM6641
• Kit Application Type: Power Management - Voltage Regulator
• Application Sub Type: Monolithic Voltage Regulator
• Kit Contents: Board
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: PM6641
• Other names: 497-8425

PM6641
In order to obtain the typical integrative loop transfer function the signal stag e must
compensate for the power stage pole (due to the output capacitor and the load) and zero
(above the loop bandwidth if ceramic output capacitors are selected). The signal stage
transfer function is:
Equation 2
Where g
due to the output resistor divider (0.8 V / Vout). The external compensation network (R
and C
●
●
●
The control loop gain is obtained by multiplying G(s) by H(s):
Equation 3
This model provides good results if the control loop cut-off frequency f
fsw/10.
One zero, to compensate the power stage pole:
One pole in order to delete the static output voltage error;
One pole, if necessary, in order to compensate the high frequency zero due to the
output capacitor ESR:
RO
M
) introduces:
is the power stage transconductance, K
G
LOOP
(
) s
=
g
m
( G
K
L
) s
α
Doc ID 13510 Rev 3
=
sC
g
C
m
C
⎛
⎜
⎜
⎝
K
C
sC
R
L
C
(
sC
α
C
RO
Ro
sC
=
C
R
R
R
C
C
C
C
C
O
⎛
⎜ ⎜
⎝
=
+
sC
(
+
R
C
sC
C
1
C
O
Ro
O
)
Ro
C
R
L
C
+
R
R
ES
is a design parameter and α is the gain
R
+
C
C
ES
1
+
⎞
⎟
⎟
⎠
+
)
C
⋅
1
C
sC
Ro
C
(
O
sC
+
(
R
1
⎞
⎟ ⎟
⎠
O
ES
R
ES
+
R
CO
+
O
1
Device description
)
)
is lower than about
+
1
R
O
c
25/47
, C
c