AD9755-EB Analog Devices Inc, AD9755-EB Datasheet - Page 13

• Manufacturer Part Number: AD9755-EB
• Description: BOARD EVAL FOR AD9755
• Manufacturer: Analog Devices Inc
• Series: TxDAC+®r

Specifications of AD9755-EB

• Rohs Status: RoHS non-compliant
• Number Of Dac's: 1
• Number Of Bits: 14
• Outputs And Type: 1, Differential
• Sampling Rate (per Second): 300M
• Data Interface: Parallel
• Settling Time: 11ns
• Dac Type: Current
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9755

REV. B
INTERLEAVED (2 ) MODE WITH PLL DISABLED
The relationship between the internal and external clocks in this
mode is shown in Figure 11. A clock at the output update data
rate (2× the input data rate) must be applied to the CLK inputs.
Internal dividers then create the internal 1× clock necessary for
the input latches. Although the input latches are updated on the
rising edge of the delayed internal 1× clock, the setup-and-hold
times given in the Digital Specifications table are with respect to
the rising edge of the external 2× clock. With the PLL disabled,
a load-dependent delayed version of the 1× clock is present at
the PLLLOCK pin. This signal can be used to synchronize the
external data.
Updates to the data at input Ports 1 and 2 should be synchro-
nized to the specific rising edge of the external 2× clock that
corresponds to the rising edge of the 1× internal clock, as shown
in Figure 11. To ensure synchronization, a Logic 1 must be
momentarily applied to the RESET pin. Doing this and return-
ing RESET to Logic 0 brings the 1× clock at PLLLOCK to a
Logic 1. On the next rising edge of the 2× clock, the 1× clock
will go to Logic 0. On the second rising edge of the 2× clock, the
1× clock (PLLLOCK) will again go to Logic 1, as well as update
the data in both of the input latches. The details of this are
shown in Figure 12.
For proper synchronization, sufficient delay must be present
between the time RESET goes low and the rising edge of the 2×
clock. RESET going low must occur either at least t
the rising edge of the 2× clock, or t
case, the immediately occurring CLK rising edge will cause
PLLLOCK to go low. In the second case, the next CLK rising
edge will toggle PLLLOCK.
Figure 11. Timing Requirements, Interleaved (2 × ) Mode
with PLL Disabled
@ PLLLOCK
Figure 12. Reset Function Timing with PLL Disabled
EXTERNAL
EXTERNAL
INTERNAL
DELAYED
DATA IN
PORT 2
PORT 1
1
1
2
CLK
CLK
CLK
EXTERNAL
2
PLLLOCK
CLOCK
RESET
t
DATA X
DATA Y
I
OUTA
S
ON THESE EDGES
INPUT LATCHES
t
t
t
OR I
H
DATA ENTERS
LPW
D
t
RS
OUTB
= 0.2ns
t
RH
PD
DATA ENTERS
INPUT LATCHES
ON THIS EDGE
ns afterwards. In the first
DATA X
t
RH
= 1.2ns
t
PD
RS
DATA Y
ns before
–13–
NONINTERLEAVED MODE WITH PLL DISABLED
If the data at only one port is required, the AD9755 interface
can operate as a simple double buffered latch with no interleaving.
On the rising edge of the 1× clock, input latch 1 or 2 is updated
with the present input data (depending on the state of DIV0/
DIV1). On the next rising edge, the DAC latch is updated and a
time t
represents the AD9755 timing in this mode.
DAC TRANSFER FUNCTION
The AD9755 provides complementary current outputs, I
I
when all bits are high (i.e., DAC CODE = 16383) while I
the complementary output, provides no current. The current
output appearing at I
input code and I
where DAC CODE = 0 to 16383 (i.e., decimal representation).
As mentioned previously, I
current, I
V
The two current outputs typically drive a resistive load directly
or via a transformer. If dc coupling is required, I
should be directly connected to matching resistive loads, R
that are tied to analog common, ACOM. Note that R
represent the equivalent load resistance seen by I
as would be the case in a doubly terminated 50 Ω or 75 Ω cable.
The single-ended voltage output appearing at the I
I
Note that the full-scale value of V
exceed the specified output compliance range to maintain specified
distortion and linearity performance.
Substituting the values of I
expressed as
where I
OUTB
OUTB
Figure 13. Timing Requirements, Noninterleaved Mode
with PLL Disabled
REFIO
V
V
V
V
(
I
I
I
32
OUTA
OUTB
OUTFS
OUTA
OUTB
DIFF
DIFF
. I
PD
nodes is simply
, and external resistor R
OUTA
R
PORT 1 OR
1
REF
later, the DAC output reflects this change. Figure 13
LOAD
REF
DATA IN
=
=
=
CLOCK
=
=
PORT 2
=
=
(
(
{
(
, which is nominally set by a reference voltage,
=
I
provides a near full-scale current output, I
I
16383
32
I
DAC CODE
(
OUTA
OUTB
2
V
OUTA
R
REFIO
DAC CODE
×
OUTFS
SET
I
REF
I
×
×
OUTA
−
−
OUTA
t
)
R
R
S
, and can be expressed as
I
DAC CODE
R
×
OUTB
LOAD
LOAD
SET
OR I
V
REFIO
and I
t
OUTFS
OUTA
t
OUTB
H
LPW
16383
)
×
SET
−
, I
OUTB
R
16383 16384
is a function of the reference
. It can be expressed as
LOAD
OUTB
OUTA
)
×
)
is a function of both the
I
16384
, and I
OUTFS
)
and V
XX
t
PD
REF
×
OUTB
}
I
AD9755
, V
OUTFS
DATA OUT
PORT 1 OR
PORT 2
OUTA
OUTA
×
OUTA
DIFF
should not
LOAD
and I
or I
OUTA
OUTFS
can be
and
OUTB
OUTB
may
OUTB
LOAD
and
,
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
,
,