AD9755-EB Analog Devices Inc, AD9755-EB Datasheet - Page 14

• Manufacturer Part Number: AD9755-EB
• Description: BOARD EVAL FOR AD9755
• Manufacturer: Analog Devices Inc
• Series: TxDAC+®r

Specifications of AD9755-EB

• Rohs Status: RoHS non-compliant
• Number Of Dac's: 1
• Number Of Bits: 14
• Outputs And Type: 1, Differential
• Sampling Rate (per Second): 300M
• Data Interface: Parallel
• Settling Time: 11ns
• Dac Type: Current
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9755

AD9755
Equations 7 and 8 highlight some of the advantages of operating
the AD9755 differentially. First, the differential operation will
help cancel common-mode error sources associated with I
and I
differential code-dependent current and subsequent voltage, V
is twice the value of the single-ended voltage output (i.e., V
or V
Note that the gain drift temperature performance for a single-
ended (V
AD9755 can be enhanced by selecting temperature tracking
resistors for R
ship, as shown in Equation 8.
ANALOG OUTPUTS
The AD9755 produces two complementary current outputs,
I
differential operation. I
complementary single-ended voltage outputs, V
via a load resistor, R
8 in the DAC Transfer Function section. The differential volt-
age, V
converted to a single-ended voltage via a transformer or differen-
tial amplifier configuration. The ac performance of the AD9755
is optimum and is specified using a differential transformer-
coupled output in which the voltage swing at I
limited to ± 0.5 V. If a single-ended unipolar output is desirable,
I
The distortion and noise performance of the AD9755 can be
enhanced when it is configured for differential operation. The
common-mode error sources of both I
significantly reduced by the common-mode rejection of a trans-
former or differential amplifier. These common-mode error
sources include even-order distortion products and noise. The
enhancement in distortion performance becomes more significant
as the frequency content of the reconstructed waveform increases.
This is due to the first order cancellation of various dynamic
common-mode distortion mechanisms, digital feedthrough,
and noise.
Performing a differential-to-single-ended conversion via a
transformer also provides the ability to deliver twice the recon-
structed signal power to the load (i.e., assuming no source
termination). Since the output currents of I
complementary, they become additive when processed differen-
tially. A properly selected transformer will allow the AD9755 to
provide the required power and voltage levels to different loads.
Refer to Applying the AD9755 section for examples of various
output configurations.
The output impedance of I
equivalent parallel combination of the PMOS switches associated
with the current sources and is typically 100 kΩ in parallel with
5 pF. It is also slightly dependent on the output voltage (i.e.,
V
result, maintaining I
I-V op amp configuration will result in the optimum dc linearity.
Note that the INL/DNL specifications for the AD9755 are
measured with I
an op amp.
OUTA
OUTA
OUTA
OUTB
OUTB
DIFF
and I
should be selected as the output, with I
and V
), thus providing twice the signal power to the load.
OUTA
, existing between V
such as noise, distortion, and dc offsets. Second, the
OUTB
OUTB
LOAD
and V
OUTA
, that may be configured for single-ended or
) due to the nature of a PMOS device. As a
and R
OUTA
LOAD
OUTB
and I
OUTA
, as described by Equations 5 through
SET
) or differential output (V
and/or I
OUTB
OUTA
and I
due to their ratiometric relation-
OUTA
maintained at virtual ground via
and I
OUTB
OUTB
and V
OUTB
OUTA
at a virtual ground via an
can be converted into
OUTB
is determined by the
OUTA
and I
OUTB
OUTA
, can also be
OUTA
OUTB
and I
grounded.
DIFF
and I
and V
OUTB
can be
) of the
OUTB
OUTA
OUTB
OUTA
are
DIFF
is
,
,
–14–
I
compliance range that must be adhered to in order to achieve
optimum performance. The negative output compliance range
of –1.0 V is set by the breakdown limits of the CMOS process.
Operation beyond this maximum limit may result in a breakdown
of the output stage and affect the reliability of the AD9755.
The positive output compliance range is slightly dependent on
the full-scale output current, I
nominal 1.25 V for an I
2 mA. The optimum distortion performance for a single-ended
or differential output is achieved when the maximum full-scale
signal at I
requiring the AD9755’s output (i.e., V
extend its output compliance range should size R
Operation beyond this compliance range will adversely affect the
AD9755’s linearity performance and subsequently degrade its
distortion performance.
DIGITAL INPUTS
The AD9755’s digital inputs consist of two channels of 14 data
input pins each and a pair of differential clock input pins. The
14-bit parallel data inputs follow standard straight binary coding
where DB13 is the most significant bit (MSB) and DB0 is the
least significant bit (LSB). I
current when all data bits are at Logic 1. I
mentary output with the full-scale current split between the two
outputs as a function of the input code.
The digital interface is implemented using an edge-triggered
master slave latch. With the PLL active or disabled, the DAC
output is updated twice for every input latch rising edge, as
shown in Figures 7 and 11. The AD9755 is designed to support
an input data rate as high as 150 MSPS, giving a DAC output
update rate of 300 MSPS. The setup-and-hold times can also be
varied within the clock cycle as long as the specified minimum
times are met. Best performance is typically achieved when the
input data transitions on the falling edge of a 50% duty cycle clock.
The digital inputs are CMOS compatible with logic thresholds,
V
supply (DVDD) or
The internal digital circuitry of the AD9755 is capable of oper-
ating over a digital supply range of 3.0 V to 3.6 V. As a result,
the digital inputs can also accommodate TTL levels when DVDD
is set to accommodate the maximum high level voltage of the
TTL drivers V
ensures proper compatibility with most TTL logic families.
Figure 14 shows the equivalent digital input circuit for the data
and clock inputs.
OUTA
THRESHOLD
and I
OUTA
OUTB
, set to approximately half the digital positive
Figure 14. Equivalent Digital Input
OH
and I
V
(max). A DVDD of 3.0 V to 3.6 V typically
THRESHOLD
also have a negative and positive voltage
DIGITAL
INPUT
OUTB
OUTFS
does not exceed 0.5 V. Applications
OUTA
=
= 20 mA to 1.00 V for an I
OUTFS
DVDD
produces a full-scale output
. It degrades slightly from its
OUTA
2 20%
OUTB
(
DVDD
±
and/or V
produces a comple-
LOAD
)
accordingly.
OUTB
OUTFS
REV. B
) to
=