MPC8315E-RDBA Freescale Semiconductor, MPC8315E-RDBA Datasheet
MPC8315E-RDBA
Specifications of MPC8315E-RDBA
Related parts for MPC8315E-RDBA
MPC8315E-RDBA Summary of contents
Page 1
... In addition to the e300 core, the SoC © Freescale Semiconductor, Inc., 2009. All rights reserved. Document Number: MPC8315EEC ™ II Pro Processor 1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2. MPC8315E Features . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 8 4. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 14 5. Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 17 7. DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . 18 8 ...
Page 2
... The MPC8315E offers additional high-speed interconnect support with dual integrated SATA 3 Gbps interfaces and dual single-lane PCI Express interfaces. When not used for PCI Express, the SerDes interface may be configured to support SGMII. The MPC8315E security engine (SEC 3.3) allows CPU-intensive cryptographic operations to be offloaded from the main CPU core. A block diagram of the ...
Page 3
... Software-compatible with the Freescale processor families implementing the PowerPC Architecture • Performance monitor 2.2 Serial Interfaces The following interfaces are supported in the MPC8315E. • Two enhanced TSECs (eTSECs) • Two Ethernet interfaces using one RGMII/MII/RMII/RTBI or SGMII (no GMII) 2 • Dual UART, one I C, and one SPI interface 2 ...
Page 4
... Up to 128 time slots, where each slot can be programmed to be active or inactive • 16-bit word widths • The TDM Transmitter Sync Signal (TFS), Transmitter Clock Signal (TCK) and Receiver Clock • Signal (RCK) can be configured as either input or output MPC8315E PowerQUICC 4 ™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor ...
Page 5
... Dedicated descriptor based DMA engine per interface with separate read and write channels 2.9 Dual Serial ATA (SATA) Controllers The SATA controllers have the following features: • Designed to comply with Serial ATA Rev 2.5 Specification MPC8315E PowerQUICC Freescale Semiconductor ™ II Pro Processor Hardware Specifications, Rev. 0 MPC8315E Features 5 ...
Page 6
... Power Management Controller (PMC) The MPC8315E supports a range of power management states that significantly lower power consumption under the control of the power management controller. The PMC includes the following features: • Provides power management when the device is used in both PCI host and agent modes • ...
Page 7
... PCI Express-based PME events are not supported 2.13 Serial Peripheral Interface (SPI) The serial peripheral interface (SPI) allows the MPC8315E to exchange data between other PowerQUICC family chips, Ethernet PHYs for configuration, and peripheral devices such as EEPROMs, real-time clocks, A/D converters, and ISDN devices. ...
Page 8
... Electrical Characteristics This section provides the AC and DC electrical specifications and thermal characteristics for the MPC8315E, which is currently targeted to these specifications. Some of these specifications are independent of the I/O cell, but they are included for complete reference. These are not purely I/O buffer design specifications ...
Page 9
... LVDD means LVDD1_OFF and LVDD2_ON 3.1.2 Power Supply Voltage Specification Table 2 provides the recommended operating conditions for theMPC8315E. Note that the values in are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed. Table 2. Recommended Operating Conditions ...
Page 10
... DDR2 controller Standard I/O voltage Standard I/O voltage Standard I/O voltage Standard I/O voltage Standard I/O voltage Standard I/O voltage eTSEC/USBdr I/O supply eTSEC I/O supply Analog and digital ground MPC8315E PowerQUICC 10 Recommended Symbol 1 Value USB_PLL_PWR1 1.0 ± USB_PLL_GND 0.0 USB_VDDA_BIAS 3.3 ± ...
Page 11
... Junction temperature range Note: 1. The NVDDx_ON are static power supplies and can be connected together. 2. The NVDDx_OFF are switchable power supplies and can be connected together. 3. Minimum Temperature is specified with T Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8315E. G/L/NVDD + 20% G/L/NVDD + 5% G/L/NVDD V IH GND – ...
Page 12
... Power Sequencing The MPC8315E does not require the core supply voltage (VDD and VDDC) and I/O supply voltages (GVDD, LVDDx_ON, LVDDx_OFF, NVDDx_ON and NVDDx_OFF applied in any particular order. During the power ramp up, before the power supplies are stable, if the I/O voltages are supplied before the core voltage, there may be a period of time when all input and output pins be actively driven and cause contention and/or excessive current ...
Page 13
... The switchable and continuous supplies can be combined when the D3 warm mode is not used. The SATA power supplies VDD33PLL and VDD33ANA should go high after NVDD3_OFF supply and go low before NVDD3_OFF supply. The NVDD3_OFF voltage levels should not drop below the VDD33PLL, VDD33ANA voltages at any time. MPC8315E PowerQUICC Freescale Semiconductor CAUTION Figure 4 ...
Page 14
... Figure 5. SATA Power Supplies Table 4. MPC8315E Power Dissipation CSB Frequency (MHz) Typical 133 1.116 133 1.142 133 1.167 = 1.05V, a junction temperature 1.05V, and an artificial smoker test running at room temperature. dd Table 5. MPC8315E Power Dissipation LVDD1_OFF/ LVDD2 LVDD2_ON _ON (3.3 V) (3.3V) (3.3V) 0.323 — ...
Page 15
... PCIe two 2.5 GHz — x1lane SATA two 3.0 GHz — ports Other I/O — — 5 Clock Input Timing This section provides the clock input DC and AC electrical characteristics for the MPC8315E. MPC8315E PowerQUICC Freescale Semiconductor LVDD1_OFF/ LVDD2 LVDD2_ON _ON (3.3 V) (3.3V) (3.3V) — ...
Page 16
... USB_CR_CLK_IN input current SATA_CLK_IN input current 5.2 AC Electrical Characteristics The primary clock source for the MPC8315E can be one of two inputs, SYS_CLKIN or PCI_CLK, depending on whether the device is configured in PCI host or PCI agent mode. input (SYS_CLKIN/PCI_CLK) AC timing specifications for the MPC8315E. Table 7. SYS_CLKIN AC Timing Specifications ...
Page 17
... This section describes the DC and AC electrical specifications for the reset initialization timing and electrical requirements of the MPC8315E. 6.1 RESET DC Electrical Characteristics Table 8 provides the DC electrical characteristics for the RESET pins of the MPC8315E. Table 8. RESET Pins DC Electrical Characteristics Characteristic Input high voltage Input low voltage ...
Page 18
... DDR and DDR2 SDRAM This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the MPC8315E. Note that DDR SDRAM is GVDD(typ) = 2.5 V and DDR2 SDRAM is GVDD(typ) = 1.8 V. 7.1 DDR and DDR2 SDRAM DC Electrical Characteristics Table 11 provides the recommended operating conditions for the DDR2 SDRAM component(s) of the MPC8315E when GVDD(typ ...
Page 19
... Delta input/output capacitance: DQ, DQS Note: 1. This parameter is sampled. GVDD = 1.8 V ± 0.090 MHz, T Table 13 provides the recommended operating conditions for the DDR SDRAM component(s) of the MPC8315E when GVDD(typ) = 2.5 V Table 13. DDR SDRAM DC Electrical Characteristics for GVDD(typ) = 2.5 V Parameter/Condition I/O supply voltage I/O reference voltage ...
Page 20
... Table 17 lists the input AC timing specifications for the DDR SDRAM when GVDD(typ)=2.5 V. Table 17. DDR SDRAM Input AC Timing Specifications for 2.5 V Interface At recommended operating conditions with GVDD of 2.5V ± 200 mV Parameter AC input low voltage AC input high voltage MPC8315E PowerQUICC 20 Symbol DIO = 25° ...
Page 21
... CISKEW Figure 6 shows the DDR SDRAM input AC timing for the tolerated MDQS to MDQ skew (t MCK[n] MCK[n] MDQS[n] MDQ[x] MPC8315E PowerQUICC Freescale Semiconductor Symbol Min t CISKEW 266 MHz –875 200 MHz –1250 )) where T is the clock period and abs(t ...
Page 22
... DQSS override bits in the TIMING_CFG_2 register. This is typically set to the same delay as the clock adjust in the CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set to the same adjustment value. See the MPC8315E PowerQUICC II Pro Host Processor Reference Manual for a description and understanding of the timing modifications enabled by use of these bits. ...
Page 23
... MCK MDQS MDQS Figure 8 shows the DDR and DDR2 SDRAM output timing diagram. MCK MCK ADDR/CMD Write A0 MDQS[n] MDQ[x] Figure 8. DDR and DDR2 SDRAM Output Timing Diagram MPC8315E PowerQUICC Freescale Semiconductor t MCK t = 0.6 ns DDKHMH(max –0.6 ns DDKHMH(min) Figure 7. Timing Diagram for t DDKHMH ...
Page 24
... The middle of a start bit is detected as the eighth sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are sampled each sixteenth sample. 9 Ethernet: Three-Speed Ethernet, MII Management This section provides the AC and DC electrical characteristics for three-speed, 10/100/1000, and MII management. MPC8315E PowerQUICC Ω Figure 9. DDR AC Test Load Table 22 ...
Page 25
... Supply voltage 3.3 V Output high voltage Output low voltage Input high voltage Input low voltage Input high current Input low current Note: 1. The symbol this case, represents the LV IN MPC8315E PowerQUICC Freescale Semiconductor Section 9.3, “Ethernet Management Symbol Conditions LVDD — — –4.0 mA ...
Page 26
... Note that, in general, MTX the clock reference symbol representation is based on two to three letters representing the clock of a particular functional. For example, the subscript of t MTX used with the appropriate letter: R (rise (fall). MPC8315E PowerQUICC 26 Symbol Conditions LVDD — ...
Page 27
... For example, the subscript of t MRX used with the appropriate letter: R (rise (fall). Figure 11 provides the AC test load for eTSEC. Output MPC8315E PowerQUICC Freescale Semiconductor t MTX t t MTXH ...
Page 28
... RMII transmit timing (RMT) for the time t (X). Note that, in general, the clock reference symbol representation is based on two to three letters representing the clock of a particular functional. For example, the subscript of t times, the latter convention is used with the appropriate letter: R (rise (fall). MPC8315E PowerQUICC 28 t MRX ...
Page 29
... Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of t times, the latter convention is used with the appropriate letter: R (rise (fall). Figure 14 provides the AC test load. Output MPC8315E PowerQUICC Freescale Semiconductor t RMX t t ...
Page 30
... This symbol is used to represent the external GTX_CLK125 and does not follow the original symbol naming convention. GTX_CLK supply voltage is fixed at 3.3V inside the chip. If PHY supplies a 2.5 V Clock signal on this input, set TSCOMOBI bit of System I/O configuration register (SICRH See the MPC8315E PowerQUICC™ II Pro Integrated Host Processor Family Reference Manual . ...
Page 31
... The MDC and MDIO are defined to operate at a supply voltage of 3.3 V. The DC electrical characteristics for MDIO and MDC are provided in Table 30. MII Management DC Electrical Characteristics Powered at 3.3 V Parameter Supply voltage (3.3 V) Output high voltage Output low voltage Input high voltage Input low voltage MPC8315E PowerQUICC Freescale Semiconductor t RGTH t SKRGT TXD[8:5] TXD[3:0] TXD[7:4] ...
Page 32
... R (rise (fall). 2. This parameter is dependent on the csb_clk speed (that is, for a csb_clk of 133 MHz, the maximum frequency is 4.16 MHz and the minimum frequency is 0.593 MHz). 3. This parameter is dependent on the csb_clk speed (that is, for a csb_clk of 133 MHz, the delay is 60 ns). MPC8315E PowerQUICC 32 Symbol Conditions ...
Page 33
... Input high voltage Input low voltage Input current 9.4.2 1588 Timer AC Specifications Table 33 provides the 1588 timer AC specifications. Parameter Timer clock cycle time Input setup to timer clock Input hold from timer clock MPC8315E PowerQUICC Freescale Semiconductor t MDC t t MDCF MDCH t MDDVKH t ...
Page 34
... SGMII Interface Electrical Characteristics Each SGMII port features a 4-wire AC-Coupled serial link from the dedicated SerDes interface of MPC8315E as shown in Figure output pin of the SerDes transmitter differential pair features 50-Ω output impedance. Each input of the SerDes receiver differential pair features 50-Ω on-die termination to XCOREVSS. The reference circuit of the SerDes transmitter and receiver is shown in When an eTSEC port is configured to operate in SGMII mode, the parallel interface’ ...
Page 35
... TXEQA (for SerDes lane TXEQE (for SerDes lane E) bit field of MPC8315E’s SerDes Control Register 0: • The LSbits (bit [1:3]) of the above bit field is set based on the equalization setting shown in table. ...
Page 36
... Figure 18. 4-Wire AC-Coupled SGMII Serial Link Connection Example MPC8315E SGMII SerDes Interface Transmitter Figure 19. SGMII Transmitter DC Measurement Circuit Table 36. SGMII DC Receiver Electrical Characteristics Parameter Supply Voltage DC Input voltage range Input differential voltage MPC8315E PowerQUICC 36 TXn 50 Ω RXm Ω TXn RXm RXn ...
Page 37
... The concept of this parameter is equivalent to the Electrical Idle Detect Threshold parameter in PCI Express. Refer to PCI Express Differential Receiver (RX) Input Specifications section for further explanation. 4. The EQ shown in the table refers to the RXEQA or RXEQE bit field of MPC8315E’s SerDes Control Register also referred to as peak to peak AC common mode voltage. ...
Page 38
... Each UI is 800 ps ± 100 ppm. 3. The external AC coupling capacitor is required. It’s recommended to be placed near the device transmitter outputs Refer to RapidIO 1x/4x LP Serial Physical Layer Specification for interpretation of jitter specifications. MPC8315E PowerQUICC 38 Figure 20 shows the SGMII Receiver Input Compliance Symbol ...
Page 39
... RX_DIFFp-p-max 0 Figure 20. SGMII Receiver Input Compliance Mask Figure 21. SGMII AC Test/Measurement Load 10 USB 10.1 USB Dual-Role Controllers This section provides the AC and DC electrical specifications for the USB-ULPI interface. MPC8315E PowerQUICC Freescale Semiconductor 0.275 0.4 0.6 Time (UI) ™ II Pro Processor Hardware Specifications, Rev. 0 ...
Page 40
... For purposes of active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. Figure 22 and Figure 23 provide the AC test load and signals for the USB, respectively. Output MPC8315E PowerQUICC 40 Table 39. USB DC Electrical Characteristics Symbol ...
Page 41
... Input low voltage Table 42 provides the USB clock input (USB_CLK_IN) AC timing specifications. Table 42. USB_CLK_IN AC Timing Specifications Parameter/Condition Frequency range Clock frequency tolerance Reference clock duty cycle Total input jitter/Time interval error MPC8315E PowerQUICC Freescale Semiconductor t USIVKH t t USKHOX USKHOV Figure 23. USB Signals ...
Page 42
... NVDD 11.2 Local Bus AC Electrical Specifications Table 44 describes the general timing parameters of the local bus interface of the MPC8315E. Table 44. Local Bus General Timing Parameters Parameter Local bus cycle time Input setup to local bus clock Input hold from local bus clock LALE output fall to LAD output transition (LATCH hold time) ...
Page 43
... For active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. Figure 24 provides the AC test load for the local bus. Output MPC8315E PowerQUICC Freescale Semiconductor 1 Symbol t ...
Page 44
... Figure 25. Local Bus Signals, Nonspecial Signals Only LCLK T1 T3 GPCM Mode Output Signals: LCS[0:3]/LWE UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:15] UPM Mode Output Signals: LCS[0:3]/LBS[0:1]/LGPL[0:5] Figure 26. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV MPC8315E PowerQUICC 44 t LBIVKH t LBKHOV t LBKHOZ t LBKHOV t LBOTOT t ...
Page 45
... Table 45 provides the DC electrical characteristics for the IEEE 1149.1 (JTAG) interface. Table 45. JTAG Interface DC Electrical Characteristics Characteristic Input high voltage Input low voltage Input current Output high voltage Output low voltage Output low voltage MPC8315E PowerQUICC Freescale Semiconductor t LBKHOZ t LBKHOV t LBIVKH t t ...
Page 46
... R (rise (fall). 3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only. 4. Non-JTAG signal input timing with respect Non-JTAG signal output timing with respect Guaranteed by design and characterization. MPC8315E PowerQUICC 46 Figure 29 Table 2) ...
Page 47
... Figure 28 provides the AC test load for TDO and the boundary-scan outputs of the MPC8315E. Output Figure 28. AC Test Load for the JTAG Interface Figure 29 provides the JTAG clock input timing diagram. JTAG External Clock Figure 29. JTAG Clock Input Timing Diagram Figure 30 provides the TRST timing diagram. ...
Page 48
... I2KLKV t I2KHKL C I ™ II Pro Processor Hardware Specifications, Rev JTIXKH Input Data Valid Output Data Valid 2 C interface of the MPC8315E. Min Max Unit 0.7 × NVDD NVDD + 0.3 V 0.3 × NVDD –0.3 V 0.2 × NVDD 0 V 0.8 × NVDD NVDD + 0 0.1 × ...
Page 49
... Output voltage (open drain or open collector) condition = 3 mA sink current capacitance of one bus line in pF See the MPC8315E PowerQUICC II Pro Integrated Host Processor Reference Manual for information on the digital filter used. 4. I/O pins obstruct the SDA and SCL lines if NVDD is switched off ...
Page 50
... For rise and fall times, the latter convention is used I2C with the appropriate letter: R (rise (fall). 2. MPC8315E provides a hold time of at least 300 ns for the SDA signal (referred to the V undefined region of the falling edge of SCL. 3. The maximum t ...
Page 51
... IN 14.2 PCI AC Electrical Specifications This section describes the general AC timing parameters of the PCI bus. Note that the PCI_CLK or PCI_SYNC_IN signal is used as the PCI input clock depending on whether the MPC8315E is configured as a host or agent device. Table 50 . Table 50. PCI AC Timing Specifications at 66 MHz ...
Page 52
... Input timings are measured at the pin. Figure 35 provides the AC test load for PCI. Output Figure 36 shows the PCI input AC timing conditions. CLK Input Figure 36. PCI Input AC Timing Measurement Conditions MPC8315E PowerQUICC 52 1 Symbol Min t — PCKHOV t 2 ...
Page 53
... Differential Output Voltage, V The Differential Output Voltage (or Swing) of the transmitter, V the two complimentary output voltages: V negative. 3. Differential Input Voltage, V The Differential Input Voltage (or Swing) of the receiver, V two complimentary input voltages Differential Peak Voltage, V MPC8315E PowerQUICC Freescale Semiconductor t PCKHOV (or Differential Output Swing): OD – V The V TXn TXn ...
Page 54
... TD) is 500 mV p-p, which is referred as the single-ended swing for each signal. In this example, since the differential signaling environment is fully symmetrical, the transmitter output’s differential swing (V ) has the same amplitude as each signal’s single-ended swing. The differential output signal ranges OD MPC8315E PowerQUICC – B| Volts. DIFFp DIFFp-p ...
Page 55
... XCOREVSS DC exceeds the maximum input current limitations, then it must be AC-coupled off-chip. • The input amplitude requirement — This requirement is described in detail in the following sections. MPC8315E PowerQUICC Freescale Semiconductor is 500 mV in one phase and –500 mV in the other 500 mV. The peak-to-peak differential voltage (V DIFFp ™ ...
Page 56
... Figure 39. Receiver of SerDes Reference Clocks 15.2.2 DC Level Requirement for SerDes Reference Clocks The DC level requirement for the MPC8315E SerDes reference clock inputs is different depending on the signaling mode used to connect the clock driver chip and SerDes reference clock inputs as described below. • ...
Page 57
... Figure 42. Single-Ended Reference Clock Input DC Requirements 15.2.3 Interfacing With Other Differential Signaling Levels With on-chip termination to XCOREVSS, the differential reference clocks inputs are HCSL (High-Speed Current Steering Logic) compatible DC-coupled. MPC8315E PowerQUICC Freescale Semiconductor ™ II Pro Processor Hardware Specifications, Rev. 0 High-Speed Serial Interfaces (HSSI) Vmax < ...
Page 58
... MPC8315E SerDes reference clock receiver requirement provided in this document. Figure 43 shows the SerDes reference clock connection reference circuits for HCSL type clock driver. It assumes that the DC levels of the clock driver chip is compatible with MPC8315E SerDes reference clock input’s DC requirement. HCSL CLK Driver Chip CLK_Out 33 Ω ...
Page 59
... R2 is used together with the SerDes reference clock receiver’s 50-Ω termination resistor to attenuate the LVPECL output’s differential peak level such that it meets the MPC8315E SerDes reference clock’s differential input amplitude requirement (between 200mV and 800mV differential peak). ...
Page 60
... Figure 45. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only) Figure 46 shows the SerDes reference clock connection reference circuits for a single-ended clock driver. It assumes the DC levels of the clock driver are compatible with MPC8315E SerDes reference clock input’s DC requirement. Single-Ended CLK Driver Chip 33 Ω ...
Page 61
... IH 0 –200 IL SDn_REF_CL K minus Figure 47. Differential Measurement Points for Rise and Fall Time SDn_REF_CLK SDn_REF_CLK Figure 48. Single-Ended Measurement Points for Rise and Fall Time Matching MPC8315E PowerQUICC Freescale Semiconductor Symbol Rise Edge Rate Fall Edge Rate V +200 Rise-Fall Matching Figure 47 ...
Page 62
... Note that external AC Coupling capacitor is required for the above two serial transmission protocols with the capacitor value defined in specification of each protocol section. 16 PCI Express This section describes the DC and AC electrical specifications for the PCI Express bus of the MPC8315E. 16.1 DC Requirements for PCI Express SD_REF_CLK and ...
Page 63
... Symbol Unit interval Differential peak-to-peak V TX-DIFFp-p output voltage De-Emphasized V TX-DE-RATIO differential output voltage (ratio) Minimum TX eye width T TX-EYE MPC8315E PowerQUICC Freescale Semiconductor Comments UI Each UI is 400 ps ± 300 ppm. UI does not account for Spread Spectrum Clock dictated variations 2*|V TX-DIFFp-p TX- ...
Page 64
... TX-RCV-DETECT allowed during receiver detection TX DC common mode V TX-DC-CM voltage TX short circuit current I TX-SHORT limit MPC8315E PowerQUICC 64 Comments Jitter is defined as the measurement variation of the crossing points (V TX-DIFFp relation to a recovered TX UI. A recovered calculated over 3500 consecutive unit intervals of sample data. Jitter is ...
Page 65
... Transmitter DC Z TX-DC impedance Lane-to-Lane output skew L TX-SKEW AC coupling capacitor C MPC8315E PowerQUICC Freescale Semiconductor Comments Minimum time a Transmitter must be in Electrical Idle Utilized by the Receiver to start looking for an Electrical Idle Exit after successfully receiving an Electrical Idle ordered set After sending an Electrical ...
Page 66
... Measured between 20%–80% at transmitter package pins into a test load as shown in 6. See Section 4.3.1.8 of the PCI Express Base Specifications , Rev 1.0a. 7. See Section 4.2.6.3 of the PCI Express Base Specifications , Rev 1.0a. 8. MPC8315E SerDes transmitter does not have C 16.4.2 Transmitter Compliance Eye Diagrams ...
Page 67
... Table 55. Differential Receiver (RX) Input Specifications Parameter Symbol Unit interval Differential peak-to-peak V RX-DIFFp-p output voltage Minimum receiver eye T RX-EYE width MPC8315E PowerQUICC Freescale Semiconductor = 0 mV TX-DIFF [Transition Bit 800 mV TX-DIFFp-p-MIN [De-emphasized Bit] 566 mV (3 dB) >= V >= 505 mV (4 dB) TX-DIFFp-p-MIN 0 – 0.3 UI(J ...
Page 68
... Electrical idle detect V RX-IDLE-DET-DIFFp-p threshold Unexpected Electrical Idle T RX-IDLE-DET-DIFF- Enter Detect Threshold ENTERTIME Integration Time MPC8315E PowerQUICC 68 Comments Jitter is defined as the measurement variation of the crossing points (V RX-DIFFp relation to a recovered TX UI. A recovered calculated over 3500 consecutive unit intervals of sample data. Jitter is ...
Page 69
... The input receiver eye diagram is implementation specific and is not specified. RX component designer should provide additional margin to adequately compensate for the degraded minimum Receiver eye diagram (shown in adequate combination of system simulations and the return loss measured looking into the RX package MPC8315E PowerQUICC Freescale Semiconductor Comments Skew across all lanes on a Link ...
Page 70
... The allowance of the measurement point to be within 0.2 inches of the package pins is meant to acknowledge that package/board routing may benefit from D+ and D– not being exactly matched in length at the package pin boundary. MPC8315E PowerQUICC 70 NOTE Figure 52). Note that the series capacitors, C ...
Page 71
... Figure 52. Compliance Test/Measurement Load 17 Serial ATA (SATA) The serial ATA (SATA) of the MPC8315E is designed to comply with Serial ATA 2.5 Specification. Note that the external cabled applications or long backplane applications (Gen1x & Gen2x) are not supported. 17.1 Requirements for SATA REF_CLK The reference clock for MPC8315E is a single ended input clock required for the SATA Interface operation ...
Page 72
... SATA AC Electrical Characteristics Table 57 provides the general AC parameters for the SATA interface. Table 57. SATA AC Electrical Characteristics Parameter Channel Speed 1.5G t CH_SPEED 3.0G Unit Interval 1.5G 3.0G MPC8315E PowerQUICC 72 Conditions peak to peak jitter at refClk input T L Symbol Min Typical — 1.5 3.0 — ...
Page 73
... COMWAKE Transmit Burst Length COMINIT/ COMRESET Transmit Gap Length COMWAKE Transmit Gap Length 18 Timers This section describes the DC and AC electrical specifications for the timers of the MPC8315E. 18.1 Timers DC Electrical Characteristics Table 60 provides the DC electrical characteristics for the timers pins, including TIN, TOUT, TGATE, and RTC_CLK ...
Page 74
... Timers input are required to be valid for at least t Figure 54 provides the AC test load for the Timers. Output 19 GPIO This section describes the DC and AC electrical specifications for the GPIO of the MPC8315E. 19.1 GPIO DC Electrical Characteristics Table 62 provides the DC electrical characteristics for the GPIO. ...
Page 75
... DC electrical characteristics for the external interrupt pins. Characteristic Input high voltage Input low voltage Input current Output high voltage Output low voltage Output low voltage MPC8315E PowerQUICC Freescale Semiconductor = 50 Ω Figure 55. GPIO AC Test Load Table 64. IPIC DC Electrical Characteristics Symbol ...
Page 76
... IPIC inputs and outputs are asynchronous to any visible clock. IPIC outputs should be synchronized before use by any external synchronous logic. IPIC inputs are required to be valid for at least t in edge triggered mode. 21 SPI This section describes the DC and AC electrical specifications for the SPI of the MPC8315E. 21.1 SPI DC Electrical Characteristics Table 66 provides the DC electrical characteristics for the SPI ...
Page 77
... Output Signals: SPIMISO (See Note) Note: The clock edge is selectable on SPI. Figure 57. SPI AC Timing in Slave Mode (External Clock) Diagram MPC8315E PowerQUICC Freescale Semiconductor Table 67. SPI AC Timing Specifications (first two letters of functional block)(signal)(state)(reference)(state) for outputs. For example Ω ...
Page 78
... SPIMOSI (See Note) Note: The clock edge is selectable on SPI. Figure 58. SPI AC Timing in Master Mode (Internal Clock) Diagram 22 TDM This section describes the DC and AC electrical specifications for the TDM of the MPC8315E. 22.1 TDM DC Electrical Characteristics Table 68 provides the DC electrical characteristics TDM. Characteristic ...
Page 79
... Use of the rising edge or falling edge as a reference is programmable. TDMxTCK and TDMxRCK are shown using the rising edge. Figure 51 shows the TDM receive signal timing. TDMxRCK t DMIVKH TDMxRD t DMIVKH TDMxRFS TDMxRFS (output) MPC8315E PowerQUICC Freescale Semiconductor Table 69. TDM AC Timing specifications Symbol t DMFSIXKH t DM_OUTAC t DMTKHOV t DMTKHOX ...
Page 80
... TDMxTFS (output) t DMIVKH TDMxTFS (input) 23 Package and Pin Listings This section details package parameters, pin assignments, and dimensions. The MPC8315E is available in a thermally enhanced plastic ball grid array (TEPBGA II), see MPC8315E TEPBGA II,” and Section 23.2, “Mechanical Dimensions of the TEPBGA II,” ...
Page 81
... Datum A, the seating plane, is determined by the spherical crowns of the solder balls. Figure 61. Mechanical Dimensions and Bottom Surface Nomenclature of the TEPBGA II 23.3 Pinout Listings Table 70 provides the pin-out listing for the TEPBGA II package. MPC8315E PowerQUICC Freescale Semiconductor ™ II Pro Processor Hardware Specifications, Rev. 0 Package and Pin Listings 81 ...
Page 82
... Package and Pin Listings Table 70. MPC8315E TEPBGA II Pinout Listing Signal MEMC_MDQ[0] MEMC_MDQ[1] MEMC_MDQ[2] MEMC_MDQ[3] MEMC_MDQ[4] MEMC_MDQ[5] MEMC_MDQ[6] MEMC_MDQ[7] MEMC_MDQ[8] MEMC_MDQ[9] MEMC_MDQ[10] MEMC_MDQ[11] MEMC_MDQ[12] MEMC_MDQ[13] MEMC_MDQ[14] MEMC_MDQ[15] MEMC_MDQ[16] MEMC_MDQ[17] MEMC_MDQ[18] MEMC_MDQ[19] MEMC_MDQ[20] MEMC_MDQ[21] MEMC_MDQ[22] MEMC_MDQ[23] MEMC_MDQ[24] MEMC_MDQ[25] MEMC_MDQ[26] MEMC_MDQ[27] MEMC_MDQ[28] MEMC_MDQ[29] MEMC_MDQ[30] ...
Page 83
... Table 70. MPC8315E TEPBGA II Pinout Listing (continued) Signal MEMC_MDQ[31] MEMC_MDM0 MEMC_MDM1 MEMC_MDM2 MEMC_MDM3 MEMC_MDQS[0] MEMC_MDQS[1] MEMC_MDQS[2] MEMC_MDQS[3] MEMC_MBA[0] MEMC_MBA[1] MEMC_MBA[2] MEMC_MA0 MEMC_MA1 MEMC_MA2 MEMC_MA3 MEMC_MA4 MEMC_MA5 MEMC_MA6 MEMC_MA7 MEMC_MA8 MEMC_MA9 MEMC_MA10 MEMC_MA11 MEMC_MA12 MEMC_MA13 MEMC_MA14 MEMC_MWE MEMC_MRAS MEMC_MCAS MEMC_MCS[0] MEMC_MCS[1] MPC8315E PowerQUICC ...
Page 84
... Package and Pin Listings Table 70. MPC8315E TEPBGA II Pinout Listing (continued) Signal MEMC_MCKE MEMC_MCK[0] MEMC_MCK[0] MEMC_MCK[1] MEMC_MCK[1] MEMC_MODT[0] MEMC_MODT[1] MEMC_MVREF LAD0 LAD1 LAD2 LAD3 LAD4 LAD5 LAD6 LAD7 LAD8 LAD9 LAD10 LAD11 LAD12 LAD13 LAD14 LAD15 LA16 LA17 LA18 LA19 LA20 LA21 ...
Page 85
... Table 70. MPC8315E TEPBGA II Pinout Listing (continued) Signal LA23 LA24 LA25 LCS[0] LCS[1] LCS[2] LCS[3] LWE[0] /LFWE/LBS LWE[1] LBCTL LALE LGPL0/LFCLE LGPL1/LFALE LGPL2/LFRE/LOE LGPL3/LFWP LGPL4/LGTA/LUPWAIT/LFRB LGPL5 LCLK0 LCLK1 UART_SOUT1/MSRCID0 (DDR ID)/LSRCID0 UART_SIN1/MSRCID1 (DDR ID)/LSRCID1 UART_CTS[1]/MSRCID2 (DDR ID)/LSRCID2 UART_RTS[1]/MSRCID3 (DDR ID)/LSRCID3 ...
Page 86
... Package and Pin Listings Table 70. MPC8315E TEPBGA II Pinout Listing (continued) Signal MCP_OUT IRQ[0]/MCP_IN IRQ[1] IRQ[2] IRQ[3] IRQ[4] IRQ[5]/CORE_SRESET_IN IRQ[6] /CKSTOP_OUT IRQ[7]/CKSTOP_IN CFG_CLKIN_DIV EXT_PWR_CTRL PMC_PWR_OK TCK TDI TDO TMS TRST GPIO_18/TDM_RCK GPIO_20/TDM_RD GPIO_19/TDM_RFS GPIO_21/TDM_TCK GPIO_23/TDM_TD GPIO_22/TDM_TFS PINRXMINUSA PINRXMINUSB PINRXPLUSA ...
Page 87
... Table 70. MPC8315E TEPBGA II Pinout Listing (continued) Signal PINRXPLUSB PINTXMINUSA PINTXMINUSB PINTXPLUSA PINTXPLUSB SATA_ANAVIZ SATA_CLK_IN SATA_VDD SATA_VDD SATA_VSS SATA_VSS VSSRESREF RESREF VDD33ANA VDD33PLL TEST_MODE QUIESCE HRESET PORESET SYS_XTAL_IN SYS_XTAL_OUT SYS_CLK_IN USB_XTAL_IN USB_XTAL_OUT USB_CLK_IN PCI_SYNC_OUT RTC_CLK MPC8315E PowerQUICC Freescale Semiconductor Package Pin Number ...
Page 88
... Package and Pin Listings Table 70. MPC8315E TEPBGA II Pinout Listing (continued) Signal PCI_SYNC_IN AVDD1 AVDD2 THERM0 DMA_DACK0/GPIO_13 DMA_DREQ0/GPIO_12 DMA_DONE0/GPIO_14 NC, No Connect NC, No Connect PCI_INTA PCI_RESET_OUT PCI_AD[0] PCI_AD[1] PCI_AD[2] PCI_AD[3] PCI_AD[4] PCI_AD[5] PCI_AD[6] PCI_AD[7] PCI_AD[8] PCI_AD[9] PCI_AD[10] PCI_AD[11] PCI_AD[12] PCI_AD[13] PCI_AD[14] PCI_AD[15] PCI_AD[16] ...
Page 89
... Table 70. MPC8315E TEPBGA II Pinout Listing (continued) Signal PCI_AD[19] PCI_AD[20] PCI_AD[21] PCI_AD[22] PCI_AD[23] PCI_AD[24] PCI_AD[25] PCI_AD[26] PCI_AD[27] PCI_AD[28] PCI_AD[29] PCI_AD[30] PCI_AD[31] PCI_C/BE[0] PCI_C/BE[1] PCI_C/BE[2] PCI_C/BE[3] PCI_PAR PCI_FRAME PCI_TRDY PCI_IRDY PCI_STOP PCI_DEVSEL PCI_IDSEL PCI_SERR PCI_PERR PCI_REQ0 PCI_REQ1/CPCI_HS_ES PCI_REQ2 PCI_GNT0 PCI_GNT1/CPCI_HS_LED PCI_GNT2/CPCI_HS_ENUM MPC8315E PowerQUICC ...
Page 90
... Package and Pin Listings Table 70. MPC8315E TEPBGA II Pinout Listing (continued) Signal M66EN PCI_CLK0 PCI_CLK1 PCI_CLK2 PCI_PME GPIO_24/TSEC1_COL/USBDR_TXDRXD0 GPIO_25/TSEC1_CRS/USBDR_TXDRXD1 TSEC1_GTX_CLK/USBDR_TXDRXD2 TSEC1_RX_CLK/USBDR_TXDRXD3 TSCE1_RX_DV/USBDR_TXDRXD4 TSEC1_RXD[3]/USBDR_TXDRXD5 TSEC1_RXD[2]/USBDR_TXDRXD6 TSEC1_RXD[1]/USBDR_TXDRXD7/TSEC_TMR_CLK TSEC1_RXD[0]/USBDR_NXT/TSEC_TMR_TRIG1 TSEC1_RX_ER/USBDR_DIR/TSEC_TMR_TRIG2 TSEC1_TX_CLK/USBDR_CLK GPIO_28/TSEC1_TXD[3]/TSEC_TMR_GCLK GPIO_29/TSEC1_TXD[2]/TSEC_TMR_PP1 GPIO_30/TSEC1_TXD[1]/TSEC_TMR_PP2 TSEC1_TXD[0]/USBDR_STP/TSEC_TMR_PP3 GPIO_31/TSEC1_TX_EN/TSEC_TMR_ALARM1 TSEC1_TX_ER/TSEC_TMR_ALARM2 ...
Page 91
... Table 70. MPC8315E TEPBGA II Pinout Listing (continued) Signal TSEC2_RXD[3] TSEC2_RXD[2] TSEC2_RXD[1] TSEC2_RXD[0] TSEC2_RX_ER TSEC2_TX_CLK TSEC2_TXD[3]/CFG_RESET_SOURCE[0] TSEC2_TXD[2]/CFG_RESET_SOURCE[1] TSEC2_TXD[1]/CFG_RESET_SOURCE[2] TSEC2_TXD[0]/CFG_RESET_SOURCE[3] TSEC2_TX_EN TSEC2_TX_ER TXA TXA RXA RXA TXB TXB RXB RXB SD_IMP_CAL_RX SD_REF_CLK SD_REF_CLK SD_PLL_TPD SD_IMP_CAL_TX SDAVDD SD_PLL_TPA_ANA SDAVSS USB_DP USB_DM ...
Page 92
... Package and Pin Listings Table 70. MPC8315E TEPBGA II Pinout Listing (continued) Signal USB_VBUS USB_TPA USB_RBIAS USB_PLL_PWR3 USB_PLL_GND0 & USB_PLL_GND1 USB_PLL_PWR1 USB_VSSA_BIAS USB_VDDA_BIAS USB_VSSA USB_VDDA GPIO_0/DMA_DREQ1/GTM1_TOUT1 GPIO_1/DMA_DACK1/GTM1_TIN2/GTM2_TIN1 GPIO_2/DMA_DONE1/GTM1_TGATE2/GTM2_TGAT E1 GPIO_3/GTM1_TIN3/GTM2_TIN4 GPIO_4/GTM1_TGATE3/GTM2_TGATE4 GPIO_5/GTM1_TOUT3/GTM2_TOUT1 GPIO_6/GTM1_TIN4/GTM2_TIN3 GPIO_7/GTM1_TGATE4/GTM2_TGATE3 GPIO_8/USBDR_DRIVE_VBUS/GTM1_TIN1/GTM2_ TIN2 GPIO_9/USBDR_PWRFAULT/GTM1_TGATE1/GTM2_ TGATE2 GPIO_10/USBDR_PCTL0/GTM1_TOUT2/GTM2_TOU T1 GPIO_11/USBDR_PCTL1/GTM1_TOUT4/GTM2_TOU T3 SPIMOSI/GPIO_15 SPIMISO/GPIO_16 SPICLK SPISEL/GPIO_17 ...
Page 93
... Table 70. MPC8315E TEPBGA II Pinout Listing (continued) Signal GVDD LVDD1 _OFF LVDD2 _ON NVDD1 _OFF NVDD1 _ON NVDD2 _OFF NVDD2 _ON NVDD3 _OFF NVDD4 _OFF VDD VDD1ANA VDD1IO VDDC MPC8315E PowerQUICC Freescale Semiconductor Package Pin Number Pin Type Power and Ground Supplies ...
Page 94
... Package and Pin Listings Table 70. MPC8315E TEPBGA II Pinout Listing (continued) Signal VSS VSS1ANA VSS1IO XCOREVDD XCOREVSS XPADVDD MPC8315E PowerQUICC 94 Package Pin Number Pin Type A3, A27, B3, B12, B24, B28, C6, C8, C13, C17, C21, C23, C26, D2, D7, D15, D18, D20, D22, E4, E6, E11, E24, E26, F8, ...
Page 95
... This pin should USB_VSSA_BIAS through 10K precision resistor. 9. The LB_POR_CFG_BOOT_ECC functionality for this pin is only available in MPC8315E revision 1.1. The LB_POR_CFG_BOOT_ECC is sampled only during the PORESET negation. This pin with an internal pull down resistor enables the ECC by default. To disable the ECC an external strong pull up resistor or a tri-state buffer is needed. ...
Page 96
... Clocking 24 Clocking Figure 62 shows the internal distribution of clocks within the MPC8315E. MPC8315E USB Mac USB PHY PLL mux USB_CLK_IN USB_CR_CLK_IN Crystal /1,/2 USB_CR_CLK_OUT CFG_CLKIN _DIV SYS_CLK_IN SYS_CR_CLK_IN Crystal SYS_CR_CLK_OUT eTSEC GTX_CLK125 Protocol 125-MHz source Converter PCVTR Mux SD_REF_CLK SD_REF_CLK_B + PLL - 125/100 MHz 1 Multiplication factor ...
Page 97
... SPMF and COREPLL fields in the reset configuration word low (RCWL) which is loaded at power-on reset or by one of the hard-coded reset options. See Chapter 4, “Reset, Clocking, and Initialization,” in the MPC8315E PowerQUICC II Pro Host Processor Reference Manual for more information on the clock subsystem. ...
Page 98
... If either RCWL[DDRCM] or RCWL[LBCM] are set, the system PLL VCO frequency = 2 × (CSB frequency) × (System PLL VCO Divider). The VCO divider needs to be set properly so that the System PLL VCO frequency is in the range of 450–750 MHz. MPC8315E PowerQUICC 98 Table 71. Configurable Clock Units Default Frequency ...
Page 99
... Reset High High High High 1 CFG_SYS_CLKIN_DIV doubles csb_clk if set low. 2 SYS_CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode. MPC8315E PowerQUICC Freescale Semiconductor Table 73. System PLL Multiplication Factors System PLL RCWL[SPMF] Multiplication Factor 0000 Reserved 0001 Reserved × ...
Page 100
... Suggested PLL Configurations To simplify the PLL configurations, the MPC8315E might be separated into two clock domains. The first domain contain the CSB PLL and the core PLL. The core PLL is connected serially to the CSB PLL, and has the csb_clk as its input clock. The clock domains are independent, and each of their PLLs are configured separately ...
Page 101
... Thermal (Preliminary) This section describes the thermal specifications of the MPC8315E. 25.1 Thermal Characteristics provides the package thermal characteristics for the 620 29 × TEPBGA II. Table 78 Table 78. Package Thermal Characteristics for TEPBGA II Characteristic Junction to ambient natural convection Junction to ambient natural convection ...
Page 102
... D When the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made. The application board should be similar to the thermal test condition: the component is soldered to a board with internal planes. MPC8315E PowerQUICC 102 ) + P where P DD ...
Page 103
... The heat sink choice is determined by the application environment (temperature, air flow, adjacent component power dissipation) and the physical space available. Because there is not a standard application environment, a standard heat sink is not required. MPC8315E PowerQUICC Freescale Semiconductor ) can be used to determine the junction temperature with a JT × ...
Page 104
... Thermal (Preliminary) Table 79. Heat Sinks and Junction-to-Case Thermal Resistance of MPC8315E TEPBGA II Heat Sink Assuming Thermal Grease AAVID 9.4 mm Pin Fin AAVID 9.4 mm Pin Fin AAVID 9.4 mm Pin Fin AAVID 9.4 mm Pin Fin AAVID Pin Fin AAVID Pin Fin AAVID Pin Fin AAVID Pin Fin AAVID ...
Page 105
... When attaching heat sinks to these devices, an interface material is required. The best method is to use thermal grease and a spring clip. The spring clip should connect to the printed circuit board, either to the board itself, to hooks soldered to the board plastic stiffener. Avoid attachment forces which would MPC8315E PowerQUICC Freescale Semiconductor 408-436-8770 ...
Page 106
... This section provides electrical and thermal design recommendations for successful application of the MPC8315E. 26.1 System Clocking The MPC8315E includes two PLLs. 1. The platform PLL (AVDD2) generates the platform clock from the externally supplied SYS_CLKIN input. The frequency ratio between the platform and SYS_CLKIN is selected using the platform PLL ratio configuration bits as described in Configuration.” ...
Page 107
... Due to large address and data buses, and high operating frequencies, the device can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching other components in the MPC8315E system, and the MPC8315E itself requires a clean, tightly regulated source of power. Therefore recommended that the system designer place at least one decoupling capacitor at each VDD, NVDD, GVDD, and LVDD pins of the device ...
Page 108
... Output Buffer DC Impedance The MPC8315E drivers are characterized over process, voltage, and temperature. For all buses, the driver is a push-pull single-ended driver type (open drain for I To measure Z for the single-ended drivers, an external resistor is connected from the chip pad to NVDD 0 or GND ...
Page 109
... Configuration Pin Multiplexing The MPC8315E provides the user with power-on configuration options that can be set through the use of external pull-up or pull-down resistors of 4.7 kΩ on certain output pins (see customer visible configuration pins). These pins are generally used as output only pins in normal operation. ...
Page 110
... PVR = 8085_0020 for all devices and revisions in this table. 28 Document Revision History Table 83 provides a revision history for this hardware specification. Revision Date 0 05/2009 Initial public release. MPC8315E PowerQUICC 110 Table 81. Part Numbering Nomenclature VR C Temperature Package 3 Range Blank = 0 to 105°C VR – ...
Page 111
... THIS PAGE INTENTIONALLY LEFT BLANK MPC8315E PowerQUICC Freescale Semiconductor ™ II Pro Processor Hardware Specifications, Rev. 0 Document Revision History 111 ...
Page 112
... Literature Distribution Center 1-800 441-2447 or +1-303-675-2140 Fax: +1-303-675-2150 LDCForFreescaleSemiconductor @hibbertgroup.com Document Number: MPC8315EEC Rev. 0 05/2009 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document ...