PESD3V3S4UD,115 NXP Semiconductors, PESD3V3S4UD,115 Datasheet - Page 8

• Manufacturer Part Number: PESD3V3S4UD,115
• Description: DIODE ARRAY ESD 3.3V 6-TSOP
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of PESD3V3S4UD,115

• Package / Case: 6-TSOP
• Voltage - Reverse Standoff (typ): 3.3V
• Voltage - Breakdown: 5.3V
• Power (watts): 200W
• Polarization: 4 Channel Array - Bidirectional
• Mounting Type: Surface Mount
• Polarity: Unidirectional
• Clamping Voltage: 12 V
• Operating Voltage: 3.3 V
• Breakdown Voltage: 5.6 V
• Termination Style: SMD/SMT
• Peak Surge Current: 20 A
• Peak Pulse Power Dissipation: 200 W
• Capacitance: 215 pF
• Maximum Operating Temperature: + 150 C
• Minimum Operating Temperature: - 65 C
• Dimensions: 1.7 mm W x 3.1 mm L x 1.1 mm H
• Number Of Elements: 4
• Package Type: SC-74
• Operating Temperature Classification: Military
• Reverse Breakdown Voltage: 5.3V
• Reverse Stand-off Voltage: 3.3V
• Leakage Current (max): 800uA
• Peak Pulse Current: 20A
• Test Current (it): 1mA
• Operating Temp Range: -65C to 150C
• Mounting: Surface Mount
• Pin Count: 6
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-4266-2; 934059301115; PESD3V3S4UD T/R

NXP Semiconductors
7. Application information
PESDXS4UD_SER_2
Product data sheet
The PESDxS4UD series is designed for protection of up to 4 unidirectional data lines from
the damage caused by ESD and surge pulses. The PESDxS4UD series may be used on
lines where the signal polarities are above or below ground. The PESDxS4UD series
provides a surge capability of 200 W per line for an 8/20 s waveform.
Circuit board layout and protection device placement
Circuit board layout is critical for the suppression of ESD, Electrical Fast Transient (EFT)
and surge transients. The following guidelines are recommended:
1. Place the PESDxS4UD as close to the input terminal or connector as possible.
2. The path length between the PESDxS4UD and the protected line should be
3. Keep parallel signal paths to a minimum.
4. Avoid running protected conductors in parallel with unprotected conductors.
5. Minimize all Printed-Circuit Board (PCB) conductive loops including power and
6. Minimize the length of the transient return path to ground.
7. Avoid using shared transient return paths to a common ground point.
8. Ground planes should be used whenever possible. For multilayer PCBs, use ground
Fig 10. Application diagram
minimized.
ground loops.
vias.
unidirectional protection of 4 lines
Rev. 02 — 21 August 2009
Quadruple ESD protection diode arrays in a SOT457 package
1
2
3
6
5
4
PESDxS4UD series
bidirectional protection of 3 lines
n.c.
data- or transmission lines
1
2
3
006aaa762
6
5
4
n.c.
© NXP B.V. 2009. All rights reserved.
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