PIC16F526-I/SL Microchip Technology, PIC16F526-I/SL Datasheet - Page 26

• Manufacturer Part Number: PIC16F526-I/SL
• Description: IC PIC MCU FLASH 1KX12 14SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F526-I/SL

• Core Size: 8-Bit
• Program Memory Size: 1.5KB (1K x 12)
• Core Processor: PIC
• Speed: 20MHz
• Peripherals: POR, WDT
• Number Of I /o: 11
• Program Memory Type: FLASH
• Ram Size: 67 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 3x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Controller Family/series: PIC16F
• No. Of I/o's: 12
• Eeprom Memory Size: 64Byte
• Ram Memory Size: 67Byte
• Cpu Speed: 20MHz
• No. Of Timers: 1
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 67 B
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 3 Channel
• A/d Bit Size: 8 bit
• A/d Channels Available: 3
• Height: 1.25 mm
• Length: 8.65 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2 V
• Width: 3.9 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ICE2000 - EMULATOR MPLAB-ICE 2000 POD
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

PIC16F526
EXAMPLE 5-3:
DS41326A-page 24
IGNORED
Note 1: Only a series of BSF commands will work
BSF
MOVLW EE_ADR_WRITE
MOVWF EEADR
MOVLW EE_DATA_TO_WRITE;LOAD DATA TO
MOVWF EEDATA
BSF
BSF
NOP
NOP
2: For reads, erases and writes to the Flash
to enable the memory write sequence
documented in Example 5-3. No other
sequence of commands will work, no
exceptions.
data memory, there is no need to insert a
NOP into the user code as is done on
mid-range devices. The instruction imme-
diately following the “BSF EECON,WR/RD”
will be fetched and executed properly.
FSR,5
EECON,WREN
EECON,WR
DATA MEMORY WRITE
;SWITCH TO BANK 1
;LOAD ADDRESS TO
;WRITE
;INTO EEADR
;REGISTER
;INTO EEDATA
;REGISTER
;ENABLE WRITES
;START WRITE
;SEQUENCE
;WAIT AS READ
;INSTRUCTION
;IS DECODED
;INSTRUCTION
Preliminary
5.4
Data memory can be code-protected by programming
the CPDF bit in the Configuration Word (Register 8-1)
to ‘0’.
DATA MEMORY OPERATION
DURING CODE-PROTECT
© 2007 Microchip Technology Inc.