PIC16F688T-I/SL Microchip Technology, PIC16F688T-I/SL Datasheet - Page 14

• Manufacturer Part Number: PIC16F688T-I/SL
• Description: IC MCU PIC FLASH 4KX14 14SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F688T-I/SL

• Core Size: 8-Bit
• Program Memory Size: 7KB (4K x 14)
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 12
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Controller Family/series: PIC16F
• No. Of I/o's: 12
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 256Byte
• Cpu Speed: 20MHz
• No. Of Timers: 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT14SO-1 - SOCKET TRANSITION 14SOIC 150/208AC162061 - HEADER INTRFC MPLAB ICD2 20PINAC162056 - HEADER INTERFACE ICD2 16F688
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: PIC16F688T-I/SL; PIC16F688T-I/SLTR

PIC16F688
TABLE 2-4:
DS41203E-page 12
Bank 3
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
190h
191h
192h
193h
194h
195h
196h
19Ah
19Bh
199h
19Ah
19Bh
19Ch
19Dh
19Eh
19Fh
Legend:
Note
Addr
1:
2:
INDF
OPTION_REG
PCL
STATUS
TRISA
TRISC
PCLATH
INTCON
FSR
Name
– = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
MCLR and WDT Reset does not affect the previous value data latch. The RAIF bit will be cleared upon Reset but will set again if the
mismatched exists.
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PIC16F688 SPECIAL FUNCTION REGISTERS SUMMARY BANK 3
Addressing this location uses contents of FSR to address data memory (not a physical register)
Program Counter’s (PC) Least Significant Byte
Indirect Data Memory Address Pointer
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
RAPU
Bit 7
GIE
IRP
—
—
—
INTEDG
Bit 6
PEIE
RP1
—
—
—
TRISA5
TRISC5
T0CS
Bit 5
T0IE
RP0
—
Write Buffer for upper 5 bits of Program Counter
TRISC4
TRISA4
T0SE
INTE
Bit 4
TO
TRISC3
TRISA3
Bit 3
RAIE
PSA
PD
TRISA2
TRISC2
Bit 2
T0IF
PS2
Z
TRISC1
TRISA1
Bit 1
INTF
PS1
DC
© 2009 Microchip Technology Inc.
TRISA0
TRISC0
RAIF
Bit 0
PS0
C
(2)
xxxx xxxx
1111 1111
0000 0000
0001 1xxx
xxxx xxxx
--11 1111
--11 1111
---0 0000
0000 000x
POR/BOR
Value on
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20, 117
14, 117
19, 117
13, 117
20, 117
33, 117
42, 117
19, 117
15, 117
Page
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