ATTINY13-20SSU Atmel, ATTINY13-20SSU Datasheet - Page 26

• Manufacturer Part Number: ATTINY13-20SSU
• Description: IC MCU AVR 1K FLASH 20MHZ 8SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY13-20SSU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 1KB (512 x 16)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• For Use With: ATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -

6.2.3
6.2.4
6.3
6.3.1
26
System Clock Prescaler
ATtiny13
Internal 128 kHz Oscillator
Default Clock Source
Switching Time
When this Oscillator is selected, start-up times are determined by the SUT fuses as shown in
Table
Table 6-5.
Note:
The 128 kHz internal Oscillator is a low power Oscillator providing a clock of 128 kHz. The fre-
quency depends on supply voltage, temperature and batch variations. This clock may be select
as the system clock by programming the CKSEL fuses to “11”.
When this clock source is selected, start-up times are determined by the SUT fuses as shown in
Table
Table 6-6.
The device is shipped with CKSEL = “10”, SUT = “10”, and CKDIV8 programmed. The default
clock source setting is therefore the Internal RC Oscillator running at 9.6 MHz with longest start-
up time and an initial system clock prescaling of 8. This default setting ensures that all users can
make their desired clock source setting using an In-System or High-voltage Programmer.
The ATtiny13 system clock can be divided by setting the
page
processing power is low. This can be used with all clock source options, and it will affect the
clock frequency of the CPU and all synchronous peripherals. clk
are divided by a factor as shown in
When switching between prescaler settings, the System Clock Prescaler ensures that no
glitches occur in the clock system and that no intermediate frequency is higher than neither the
clock frequency corresponding to the previous setting, nor the clock frequency corresponding to
the new setting.
SUT1..0
SUT1:0
10
00
01
00
01
10
11
11
(1)
28. This feature can be used to decrease power consumption when the requirement for
6-5.
6-6.
1. The device is shipped with this option selected.
Power-down and Power-save
Start-up Times for the Internal Calibrated RC Oscillator Clock Selection
Start-up Times for the 128 kHz Internal Oscillator
from Power-down
Start-up Time from
Start-up Time
6 CK
6 CK
6 CK
6 CK
6 CK
6 CK
Table 6-8 on page
Additional Delay from
Reset (V
14CK + 64 ms
14CK + 4 ms
Additional Delay
Reserved
Reserved
14CK + 64 ms
14CK + 4 ms
14CK
from Reset
CC
14CK
28.
= 5.0V)
“CLKPR – Clock Prescale Register” on
I/O
, clk
BOD enabled
Fast rising power
Slowly rising power
Recommended Usage
BOD enabled
Fast rising power
Slowly rising power
ADC
, clk
Recommended
CPU
Usage
, and clk
2535J–AVR–08/10
FLASH