PIC16LF723-I/ML Microchip Technology, PIC16LF723-I/ML Datasheet - Page 185

• Manufacturer Part Number: PIC16LF723-I/ML
• Description: IC PIC MCU FLASH 8KX14 28-QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF723-I/ML

• Core Size: 8-Bit
• Program Memory Size: 7KB (4K x 14)
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Type: FLASH
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 11x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Controller Family/series: PIC16LF
• Ram Memory Size: 192Byte
• No. Of Timers: 3
• No. Of Pwm Channels: 2
• Digital Ic Case Style: QFN
• Supply Voltage Range: 1.8V To
• Rohs Compliant: Yes
• Core: PIC
• Processor Series: PIC16LF
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 32 KHz
• Data Ram Size: 192 B
• On-chip Adc: Yes
• Number Of Programmable I/os: 25
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 8 bit
• A/d Channels Available: 11
• Height: 0.88 mm
• Interface Type: I2C, SCI, SPI
• Length: 6 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.3 V
• Width: 6 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

17.2.10
When the CKP bit is cleared, the SCL output is held low
once it is sampled low. therefore, the CKP bit will not
stretch the SCL line until an external I
has already asserted the SCL line low. The SCL output
will remain low until the CKP bit is set and all other
devices on the I
ensures that a write to the CKP bit will not violate the
minimum
(Figure 17-14).
FIGURE 17-14:
© 2009 Microchip Technology Inc.
SSPCON
SDA
CKP
SCL
WR
CLOCK SYNCHRONIZATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
high
2
C bus have released SCL. This
time
CLOCK SYNCHRONIZATION TIMING
requirement
DX
2
C master device
for
Master device
asserts clock
SCL
PIC16F72X/PIC16LF72X
17.2.11
While in Sleep mode, the I
addresses of data, and when an address match or
complete byte transfer occurs, wake the processor
from Sleep (if SSP interrupt is enabled).
Master device
deasserts clock
SLEEP OPERATION
2
C module can receive
DS41341E-page 185
DX-1