PIC18F23K20-I/MV Microchip Technology, PIC18F23K20-I/MV Datasheet - Page 215

• Manufacturer Part Number: PIC18F23K20-I/MV
• Description: IC MCU 8BIT 8KB FLASH 28UQFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F23K20-I/MV

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 28-UFQFN Exposed Pad
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 24
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 768 B
• Interface Type: MSSP, I2C, SPI, USART
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 4
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• A/d Bit Size: 10 bit
• A/d Channels Available: 10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

17.4.4.5
When the CKP bit is cleared, the SCL output is forced
to ‘0’. However, clearing the CKP bit will not assert the
SCL output low until the SCL output is already sam-
pled low. Therefore, the CKP bit will not assert the
SCL line until an external I
already asserted the SCL line. The SCL output will
remain low until the CKP bit is set and all other
devices on the I
ensures that a write to the CKP bit will not violate the
minimum high time requirement for SCL (see
Figure 17-12).
FIGURE 17-12:
 2010 Microchip Technology Inc.
WR
SSPCON1
SDA
SCL
CKP
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Clock Synchronization and
the CKP bit
2
C bus have deasserted SCL. This
CLOCK SYNCHRONIZATION TIMING
2
C master device has
DX
Master device
asserts clock
PIC18F2XK20/4XK20
Master device
deasserts clock
DS41303G-page 215
DX – 1