ATTINY24-20PU Atmel, ATTINY24-20PU Datasheet - Page 113
![IC MCU AVR 2K FLASH 20MHZ 14-DIP](/photos/7/39/73953/313-14-dip_sml.jpg)
ATTINY24-20PU
Manufacturer Part Number
ATTINY24-20PU
Description
IC MCU AVR 2K FLASH 20MHZ 14-DIP
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY24-20PU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
12
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
14-DIP (0.300", 7.62mm)
Processor Series
ATTINY2x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
SPI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
For Use With
ATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK505 - ADAPTER KIT FOR 14PIN AVR MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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12.11.7
12.11.8
8006K–AVR–10/10
ICR1H and ICR1L – Input Capture Register 1
TIMSK1 – Timer/Counter Interrupt Mask Register 1
The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the
ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture
can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read
simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit
registers.
• Bits 7:6 – Res: Reserved Bits
These bits are reserved in the ATtiny24/44/84 and will always read as zero.
• Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Input Capture interrupt is enabled. The
corresponding Interrupt Vector (See “Interrupts” on page 66.) is executed when the
ICF1 Flag, located in TIFR1, is set.
• Bits 4:3 – Res: Reserved Bits
These bits are reserved in the ATtiny24/44/84 and will always read as zero.
• Bit 2 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The corresponding
Interrupt Vector (see
TIFR1, is set.
• Bit 1 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The corresponding
Interrupt Vector (see
TIFR1, is set.
• Bit 0 – TOIE1: Timer/Counter1, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vector
(see
Bit
0x25 (0x45)
0x24 (0x44)
Read/Write
Initial Value
Bit
0x0C (0x2C)
Read/Write
Initial Value
“Interrupts” on page
“Accessing 16-bit Registers” on page
R/W
R
7
0
7
–
0
“Interrupts” on page
“Interrupts” on page
R/W
48) is executed when the TOV1 flag, located in TIFR1, is set.
R
6
0
6
–
0
R/W
ICIE1
R/W
5
0
5
0
R/W
48) is executed when the OCF1B flag, located in
48) is executed when the OCF1A flag, located in
4
0
R
4
–
0
ICR1[15:8]
ICR1[7:0]
105.
R/W
3
0
R
3
–
0
OCIE1B
R/W
R/W
2
0
2
0
ATtiny24/44/84
OCIE1A
R/W
R/W
1
0
1
0
R/W
TOIE1
R/W
0
0
0
0
ICR1H
TIMSK1
ICR1L
113
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