PIC18F44J10-I/P Microchip Technology, PIC18F44J10-I/P Datasheet - Page 220
![IC PIC MCU FLASH 8KX16 40DIP](/photos/6/61/66192/150-40-dip_sml.jpg)
PIC18F44J10-I/P
Manufacturer Part Number
PIC18F44J10-I/P
Description
IC PIC MCU FLASH 8KX16 40DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F24J10-ISO.pdf
(368 pages)
3.PIC18F24J10-ISO.pdf
(6 pages)
4.PIC18F24J10-ISO.pdf
(6 pages)
5.PIC18F24J10-ISO.pdf
(12 pages)
6.PIC18LF24J10-ISS.pdf
(32 pages)
7.PIC18F44J10-IPT.pdf
(358 pages)
Specifications of PIC18F44J10-I/P
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
40-DIP (0.600", 15.24mm)
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPIC/I2C/EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183022, DM183032, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
13-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162074 - HEADER INTRFC MPLAB ICD2 44TQFPMA180013 - MODULE PLUG-IN 18F45J10 44TQFPAC162067 - HEADER INTRFC MPLAB ICD2 40/28PAC164329 - MODULE SKT FOR 40DIP 18F45J10
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F44J10-I/PT
Manufacturer:
MICROCHIP
Quantity:
12 000
Company:
Part Number:
PIC18F44J10-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F44J10-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC18F24J10-ISO PDF datasheet #2
- PIC18F24J10-ISO PDF datasheet #3
- PIC18F24J10-ISO PDF datasheet #4
- PIC18F24J10-ISO PDF datasheet #5
- PIC18LF24J10-ISS PDF datasheet #6
- PIC18F44J10-IPT PDF datasheet #7
- Current page: 220 of 358
- Download datasheet (6Mb)
PIC18F45J10 FAMILY
17.8
An A/D conversion can be started by the Special Event
Trigger of the CCP2 module. This requires that the
CCP2M3:CCP2M0
programmed as ‘1011’ and that the A/D module is
enabled (ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D acquisition
and conversion and the Timer1 counter will be reset to
zero. Timer1 is reset to automatically repeat the A/D
acquisition period with minimal software overhead
TABLE 17-2:
DS39682C-page 218
INTCON
PIR1
PIE1
IPR1
PIR2
PIE2
IPR2
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
PORTA
TRISA
PORTB
TRISB
LATB
PORTE
TRISE
LATE
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1:
Name
(1)
(1)
(1)
Use of the CCP2 Trigger
These registers and/or bits are not implemented on 28-pin devices and should be read as ‘0’.
PORTB Data Direction Control Register
PORTB Data Latch Register (Read and Write to Data Latch)
GIE/GIEH PEIE/GIEL TMR0IE
A/D Result Register High Byte
A/D Result Register Low Byte
PSPIE
PSPIP
PSPIF
OSCFIF
OSCFIE
OSCFIP
ADCAL
ADFM
Bit 7
RB7
IBF
—
—
—
—
—
REGISTERS ASSOCIATED WITH A/D OPERATION
(1)
(1)
(1)
bits
CMIF
CMIE
CMIP
ADIF
ADIE
ADIP
Bit 6
OBF
RB6
—
—
—
—
—
—
—
(CCP2CON<3:0>)
TRISA5
VCFG1
ACQT2
CHS3
RCIF
RCIE
RCIP
IBOV
Bit 5
RA5
RB5
—
—
—
—
—
PSPMODE
VCFG0
ACQT1
INT0IE
Preliminary
CHS2
TXIE
TXIP
Bit 4
TXIF
be
RB4
—
—
—
—
—
—
—
SSP1IF
SSP1IE
SSP1IP
BCL1IF
BCL1IE
BCL1IP
TRISA3
PCFG3
ACQT0
CHS1
(moving ADRESH:ADRESL to the desired location).
The appropriate analog input channel must be selected
and the minimum acquisition period is either timed by
the user, or an appropriate T
the Special Event Trigger sets the GO/DONE bit (starts
a conversion).
If the A/D module is not enabled (ADON is cleared), the
Special Event Trigger will be ignored by the A/D
module, but will still reset the Timer1 counter.
RBIE
Bit 3
RA3
RB3
—
—
—
PORTE Data Latch Register
(Read and Write to Data Latch)
TMR0IF
CCP1IE
CCP1IP
CCP1IF
TRISA2
TRISE2
PCFG2
ADCS2
CHS0
Bit 2
RA2
RB2
RE2
—
—
—
GO/DONE
TMR2IF
TMR2IE
TMR2IP
TRISA1
TRISE1
PCFG1
ADCS1
INT0IF
Bit 1
© 2007 Microchip Technology Inc.
RA1
RE1
RB1
—
—
—
ACQ
time selected before
TMR1IF
TMR1IE
TMR1IP
CCP2IF
CCP2IE
CCP2IP
TRISA0
TRISE0
PCFG0
ADCS0
ADON
RBIF
Bit 0
RA0
RB0
RE0
on page
Values
Reset
43
45
45
45
45
45
45
44
44
44
46
46
46
46
46
46
46
44
44
46
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