ATTINY461A-MU Atmel, ATTINY461A-MU Datasheet - Page 134

• Manufacturer Part Number: ATTINY461A-MU
• Description: IC MCU AVR 4K FLASH 20MHZ 32QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY461A-MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Processor Series: ATTINY4x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 16
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.5.5
134
ATtiny261A/461A/861A
USIPP – USI Pin Position
Table 13-2.
• Bit 1 – USICLK: Clock Strobe
Writing a one to this bit location strobes the USI Data Register to shift one step and the counter
to increment by one, provided that the USICS1:0 bits are set to zero and by doing so the soft-
ware clock strobe option is selected. The output will change immediately when the clock strobe
is executed, i.e., in the same instruction cycle. The value shifted into the USI Data Register is
sampled the previous instruction cycle. The bit will be read as zero.
When an external clock source is selected (USICS1 = 1), the USICLK function is changed from
a clock strobe to a Clock Select Register. Setting the USICLK bit in this case will select the
USITC strobe bit as clock source for the 4-bit counter (see
• Bit 0 – USITC: Toggle Clock Port Pin
Writing a one to this bit location toggles the USCK/SCL value either from 0 to 1, or from 1 to 0.
The toggling is independent of the setting in the Data Direction Register, but if the PORT value is
to be shown on the pin the DDB2 must be set as output (to one). This feature allows easy clock
generation when implementing master devices. The bit will be read as zero.
When an external clock source is selected (USICS1 = 1) and the USICLK bit is set to one, writ-
ing to the USITC strobe bit will directly clock the 4-bit counter. This allows an early detection of
when the transfer is done when operating as a master device.
• Bits 7:1 – Res: Reserved Bits
These bits are reserved and will always read as zero.
• Bit 0 – USIPOS: USI Pin Position
Setting this bit to one changes the USI pin position. As default pins PB2:PB0 are used for the
USI pin functions, but when writing this bit to one the USIPOS bit is set the USI pin functions are
on pins PA2:PA0.
Bit
0x11 (0x31)
Read/Write
Initial Value
USICS1
1
1
1
USICS0
Relations between the USICS1:0 and USICLK Setting (Continued)
1
0
1
R
7
0
-
USICLK
R
6
0
-
0
1
1
USI Data Register Clock
Source
External, negative edge
External, positive edge
External, negative edge
R
5
0
-
R
4
0
-
R
3
0
-
Table
R
2
0
-
13-2).
4-bit Counter Clock Source
External, both edges
Software clock strobe (USITC)
Software clock strobe (USITC)
R
1
0
-
USIPOS
R/W
0
0
8197B–AVR–01/10
USIPP