ATMEGA48P-20AU Atmel, ATMEGA48P-20AU Datasheet - Page 291
![MCU AVR 4K ISP FLSH 20MHZ 32TQFP](/photos/6/91/69154/313-32-tqfp_sml.jpg)
ATMEGA48P-20AU
Manufacturer Part Number
ATMEGA48P-20AU
Description
MCU AVR 4K ISP FLSH 20MHZ 32TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA48P-20AU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP, 32-VQFP
Processor Series
ATMEGA48x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
I2C/SPI/USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Package
32TQFP
Device Core
AVR
Family Name
ATmega
Maximum Speed
20 MHz
For Use With
ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA48P-20AU
Manufacturer:
TI
Quantity:
101
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27. Memory Programming
27.1
8025L–AVR–7/10
Program And Data Memory Lock Bits
The ATmega88P/168P/328P provides six Lock bits which can be left unprogrammed (“1”) or can
be programmed (“0”) to obtain the additional features listed in
be erased to “1” with the Chip Erase command. The ATmega48P has no separate Boot Loader
section. The SPM instruction is enabled for the whole Flash if the SELFPRGEN fuse is pro-
grammed (“0”), otherwise it is disabled.
Table 27-1.
Notes:
Table 27-2.
Notes:
BLB12
BLB11
BLB02
BLB01
LB2
LB1
LB Mode
Lock Bit Byte
1
2
3
(2)
(2)
(2)
(2)
1. “1” means unprogrammed, “0” means programmed
2. Only on ATmega88P/168P/328P.
1. Program the Fuse bits and Boot Lock bits before programming the LB1 and LB2.
2. “1” means unprogrammed, “0” means programmed
Memory Lock Bits
Lock Bit Byte
Lock Bit Protection Modes
LB2
1
1
0
(1)
LB1
1
0
0
Bit No
7
6
5
4
3
2
1
0
Protection Type
No memory lock features enabled.
Further programming of the Flash and EEPROM is disabled in
Parallel and Serial Programming mode. The Fuse bits are
locked in both Serial and Parallel Programming mode.
Further programming and verification of the Flash and EEPROM
is disabled in Parallel and Serial Programming mode. The Boot
Lock bits and Fuse bits are locked in both Serial and Parallel
Programming mode.
(1)(2)
Description
–
–
Boot Lock bit
Boot Lock bit
Boot Lock bit
Boot Lock bit
Lock bit
Lock bit
ATmega48P/88P/168P
(1)
Table
Default Value
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
27-2. The Lock bits can only
(1)
291
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