ATMEGA48P-20AU Atmel, ATMEGA48P-20AU Datasheet - Page 300
ATMEGA48P-20AU
Manufacturer Part Number
ATMEGA48P-20AU
Description
MCU AVR 4K ISP FLSH 20MHZ 32TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA48P-20AU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP, 32-VQFP
Processor Series
ATMEGA48x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
I2C/SPI/USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Package
32TQFP
Device Core
AVR
Family Name
ATmega
Maximum Speed
20 MHz
For Use With
ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA48P-20AU
Manufacturer:
TI
Quantity:
101
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27.7.5
8025L–AVR–7/10
Programming the EEPROM
Figure 27-2. Addressing the Flash Which is Organized in Pages
Note:
Figure 27-3. Programming the Flash Waveforms
Note:
The EEPROM is organized in pages, see
EEPROM, the program data is latched into a page buffer. This allows one page of data to be
programmed simultaneously. The programming algorithm for the EEPROM data memory is as
follows (refer to
Data loading):
1. A: Load Command “0001 0001”.
2. G: Load Address High Byte (0x00 - 0xFF).
3. B: Load Address Low Byte (0x00 - 0xFF).
4. C: Load Data (0x00 - 0xFF).
RESET +12V
RDY/BSY
PAGEL
1. PCPAGE and PCWORD are listed in
XTAL1
1. “XX” is don’t care. The letters refer to the programming description above.
DATA
XA1
XA0
BS1
BS2
WR
OE
PROGRAM MEMORY
PROGRAM
COUNTER
0x10
PAGE
”Programming the Flash” on page 298
A
PAGE ADDRESS
WITHIN THE FLASH
ADDR. LOW
B
PCMSB
DATA LOW
C
PCPAGE
DATA HIGH
D
XX
E
PAGEMSB
ADDR. LOW
Table 27-10 on page
PCWORD
B
Table 27-9 on page
WORD ADDRESS
WITHIN A PAGE
DATA LOW
(1)
C
F
ATmega48P/88P/168P
DATA HIGH
INSTRUCTION WORD
D
for details on Command, Address and
PAGE
XX
E
295.
(1)
ADDR. HIGH
295. When programming the
G
H
PCWORD[PAGEMSB:0]:
XX
00
01
02
PAGEEND
300
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