PIC16LF72-I/ML Microchip Technology, PIC16LF72-I/ML Datasheet - Page 45

• Manufacturer Part Number: PIC16LF72-I/ML
• Description: IC PIC MCU FLASH 2KX14 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16LF72-I/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 5x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -

9.0
9.1
The Synchronous Serial Port (SSP) module is a serial
interface useful for communicating with other periph-
eral or microcontroller devices. These peripheral
devices may be Serial EEPROMs, shift registers, dis-
play drivers, A/D converters, etc. The SSP module can
operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I
An overview of I
tion on the SSP module can be found in the PIC™
Mid-Range
(DS33023).
Refer to Application Note AN578, “Use of the SSP
Module in the I
© 2007 Microchip Technology Inc.
SYNCHRONOUS SERIAL PORT
(SSP) MODULE
SSP Module Overview
MCU
2
C Multi-Master Environment.”
2
C operations and additional informa-
Family
2
C)
Reference
Manual
9.2
This
operational characteristics of the SPI module.
SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. To accomplish
communication, typically three pins are used:
• Serial Data Out (SDO)
• Serial Data In (SDI)
• Serial Clock (SCK)
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Slave Select (SS)
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits in the SSPCON register (SSPCON<5:0>)
and SSPSTAT<7:6>. These control bits allow the
following to be specified:
• Master mode (SCK is the clock output)
• Slave mode (SCK is the clock input)
• Clock Polarity (IDLE state of SCK)
• Clock edge (output data on rising/falling edge of
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
SCK)
section
SPI Mode
contains
register
PIC16F72
RC5/SDO
RC4/SDI/SDA
RC3/SCK/SCL
RA5/AN4/SS
DS39597C-page 43
definitions
and