PIC16LF72-I/ML Microchip Technology, PIC16LF72-I/ML Datasheet - Page 56

• Manufacturer Part Number: PIC16LF72-I/ML
• Description: IC PIC MCU FLASH 2KX14 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16LF72-I/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 5x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -

PIC16F72
REGISTER 10-2:
The ADRES register contains the result of the A/D con-
version. When the A/D conversion is complete, the
result is loaded into the ADRES register, the GO/DONE
bit (ADCON0<2>) is cleared, and A/D interrupt flag bit
ADIF is set. The block diagram of the A/D module is
shown in Figure 10-1.
The value in the ADRES register is not modified for a
Power-on Reset. The ADRES register will contain
unknown data after a Power-on Reset.
After the A/D module has been configured as desired,
the selected channel must be acquired before the con-
version is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine acquisition time, see Section 10.1.
After this acquisition time has elapsed, the A/D
conversion can be started.
DS39597C-page 54
bit 7-3
bit 2-0
ADCON1: A/D CONTROL REGISTER 1 (ADDRESS 9Fh)
A = Analog input
Unimplemented: Read as ‘0’
PCFG<2:0>: A/D Port Configuration Control bits
bit 7
Legend:
R = Readable bit
- n = Value at POR
PCFG2:PCFG0
U-0
—
000
001
010
011
100
101
11x
U-0
—
RA0
A
A
A
A
A
A
D
D = Digital I/O
U-0
—
RA1
W = Writable bit
‘1’ = Bit is set
A
A
A
A
A
A
D
RA2
D
D
D
A
A
A
A
U-0
—
The following steps should be followed for doing an
A/D conversion:
1.
2.
3.
4.
5.
6.
7.
RA5
D
D
D
Configure the A/D module:
• Configure analog pins/voltage reference and
• Select A/D input channel (ADCON0)
• Select A/D conversion clock (ADCON0)
• Turn on A/D module (ADCON0)
Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set GIE bit
Wait the required acquisition time.
Start conversion:
• Set GO/DONE bit (ADCON0)
Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
OR
• Waiting for the A/D interrupt
Read A/D Result register (ADRES), clear bit
ADIF if required.
For next conversion, go to step 1 or step 2 as
required. The A/D conversion time per bit is
defined as T
required before the next acquisition starts.
A
A
A
A
digital I/O (ADCON1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
V
V
V
RA3
U-0
—
REF
REF
REF
A
A
A
D
AD
V
RA3
RA3
RA3
V
V
V
V
REF
. A minimum wait of 2 T
DD
DD
DD
DD
PCFG2
R/W-0
© 2007 Microchip Technology Inc.
x = Bit is unknown
PCFG1
R/W-0
PCFG0
R/W-0
AD
bit 0
is