PIC24FJ16GA002-I/SP Microchip Technology, PIC24FJ16GA002-I/SP Datasheet - Page 142

IC PIC MCU FLASH 16K 28-DIP

PIC24FJ16GA002-I/SP

Manufacturer Part Number
PIC24FJ16GA002-I/SP
Description
IC PIC MCU FLASH 16K 28-DIP
Manufacturer
Microchip Technology
Series
PIC® 24Fr

Specifications of PIC24FJ16GA002-I/SP

Core Size
16-Bit
Program Memory Size
16KB (5.5K x 24)
Core Processor
PIC
Speed
32MHz
Connectivity
I²C, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
21
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Controller Family/series
PIC24
No. Of I/o's
21
Ram Memory Size
4KB
Cpu Speed
32MHz
No. Of Timers
5
No. Of Pwm Channels
5
Embedded Interface Type
I2C, SPI, UART
Rohs Compliant
Yes
Processor Series
PIC24FJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
4 KB
Interface Type
I2C, IrDA, SPI, UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
21
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240011, MA240013, AC164127, DM300027, DV164033, DM240002
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Package
28SPDIP
Device Core
PIC
Family Name
PIC24
Maximum Speed
32 MHz
Operating Supply Voltage
2.5|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC162088 - HEADER MPLAB ICD2 24FJ64GA004 28AC164337 - MODULE SOCKET FOR PM3 40DIPDV164033 - KIT START EXPLORER 16 MPLAB ICD2
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
PIC24FJ64GA004 FAMILY
FIGURE 14-3:
FIGURE 14-4:
DS39881B-page 140
Note
PROCESSOR 1 (SPI Enhanced Buffer Master)
Note
1:
2:
1:
2:
PROCESSOR 1 (SPI Master)
MSTEN (SPIxCON1<5>) = 1 and
Using the SSx pin in Slave mode of operation is optional.
User must write transmit data to read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory
mapped to SPIxBUF.
SPIBEN (SPIxCON2<0>) = 1
MSTEN (SPIxCON1<5>) = 1)
Using the SSx pin in Slave mode of operation is optional.
User must write transmit data to read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory
mapped to SPIxBUF.
MSb
MSb
SPI MASTER/SLAVE CONNECTION (ENHANCED BUFFER MODES)
8-Level FIFO Buffer
SPI MASTER/SLAVE CONNECTION (STANDARD MODE)
Serial Receive Buffer
Serial Transmit Buffer
Shift Register
SPIx Buffer
(SPIxBUF)
(SPIxSR)
Shift Register
SPIx Buffer
(SPIxRXB)
(SPIxBUF)
(SPIxTXB)
(SPIxSR)
LSb
LSb
SDOx
SCKx
SDIx
SDOx
SDIx
SCKx
SSx
Preliminary
Serial Clock
Serial Clock
SSEN (SPIxCON1<7>) = 1 and MSTEN (SPIxCON1<5>) = 0
SDIx
SDOx
SCKx
SSx
SCKx
SDIx
SDOx
SSx
PROCESSOR 2 (SPI Enhanced Buffer Slave)
PROCESSOR 2 (SPI Slave)
MSb
Serial Transmit Buffer
Serial Receive Buffer
MSTEN (SPIxCON1<5>) = 0 and
SSEN (SPIxCON1<7>) = 1,
SPIBEN (SPIxCON2<0>) = 1
Shift Register
SPIx Buffer
(SPIxRXB)
MSb
(SPIxTXB)
(SPIxBUF)
(SPIxSR)
8-level FIFO Buffer
Shift Register
SPIx Buffer
(SPIxBUF)
(SPIxSR)
© 2007 Microchip Technology Inc.
LSb
LSb

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