ATMEGA8515L-8AU Atmel, ATMEGA8515L-8AU Datasheet - Page 200

• Manufacturer Part Number: ATMEGA8515L-8AU
• Description: IC AVR MCU 8K 8MHZ 3V 44TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8515L-8AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: ATMEGA8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI, USART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Minimum Operating Temperature: - 40 C
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

SPI Timing
Characteristics
200
ATmega8515(L)
See Figure 87 and Figure 88 for details.
Table 97. SPI Timing Parameters
Note:
Figure 87. SPI Interface Timing Requirements (Master Mode)
(Data Output)
10
11
12
13
14
15
16
17
18
(Data Input)
(CPOL = 0)
(CPOL = 1)
1
2
3
4
5
6
7
8
9
MISO
MOSI
SCK
SCK
1. In SPI Programming mode the minimum SCK high/low period is:
SS
SS high to tri-state
SCK to out high
SCK to SS high
- 2 t
- 3 t
SCK high/low
SS low to SCK
SCK high/low
Rise/Fall time
Rise/Fall time
SS low to out
Description
SCK period
SCK period
Out to SCK
SCK to out
SCK to out
CLCL
CLCL
Setup
Setup
Hold
Hold
for f
for f
6
4
MSB
CK
CK
(1)
5
< 12 MHz
>12 MHz
MSB
Master
Master
Master
Master
Master
Master
Master
Master
Mode
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Salve
7
...
4 • t
2 • t
2 • t
Min
...
10
t
20
ck
ck
ck
ck
50% duty cycle
See Table 58
0.5 • t
2
Typ
3.6
10
10
10
10
15
15
10
SCK
LSB
1
LSB
2
2512K–AVR–01/10
Max
1.6
3
8
ns
µs
ns