ATMEGA8515L-8AU Atmel, ATMEGA8515L-8AU Datasheet - Page 73

• Manufacturer Part Number: ATMEGA8515L-8AU
• Description: IC AVR MCU 8K 8MHZ 3V 44TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8515L-8AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: ATMEGA8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI, USART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Minimum Operating Temperature: - 40 C
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

2512K–AVR–01/10
Table 36 and Table 37 relate the alternate functions of Port D to the overriding signals
shown in Figure 33 on page 64.
Table 36. Overriding Signals for Alternate Functions PD7..PD4
Table 37. Overriding Signals for Alternate Functions in PD3..PD0
Signal Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
Signal Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
PD3/INT1
0
0
0
0
0
0
INT1 ENABLE
1
INT1 INPUT
–
PD7/RD
SRE
0
SRE
1
SRE
RD
0
0
–
–
PD6/WR
SRE
0
SRE
1
SRE
WR
0
0
–
–
PD2/INT0
0
0
0
0
0
0
INT0 ENABLE
1
INT0 INPUT
–
PD5/OC1A
0
0
0
0
OC1A ENABLE
OC1A
0
0
–
–
ATmega8515(L)
PD1/TXD
TXEN0
0
TXEN0
1
TXEN0
TXD
0
0
–
–
PD4/XCK
0
0
0
0
XCK OUTPUT ENABLE
XCK OUTPUT
0
0
XCK INPUT
–
PD0/RXD
RXEN0
PORTD0 • PUD
RXEN0
0
0
0
0
0
RXD
–
73