DSPIC33FJ12GP202-I/ML Microchip Technology, DSPIC33FJ12GP202-I/ML Datasheet - Page 25

• Manufacturer Part Number: DSPIC33FJ12GP202-I/ML
• Description: IC DSPIC MCU/DSP 12K 28QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ12GP202-I/ML

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Core Frequency: 40MHz
• Core Supply Voltage: 2.75V
• Embedded Interface Type: I2C, JTAG, SPI, UART
• No. Of I/o's: 21
• Flash Memory Size: 12KB
• Supply Voltage Range: 3V To 3.6V
• Package: 28QFN EP
• Device Core: dsPIC
• Family Name: dsPIC33
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 21
• Interface Type: I2C/SPI/UART
• On-chip Adc: 10-chx10-bit|10-chx12-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164336 - MODULE SOCKET FOR PM3 28/44QFNDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

3.6.1
The 17-bit x 17-bit multiplier is capable of signed or
unsigned operation and can multiplex its output using a
scaler to support either 1.31 fractional (Q31) or 32-bit
integer results. Unsigned operands are zero-extended
into the 17th bit of the multiplier input value. Signed
operands are sign-extended into the 17th bit of the
multiplier input value. The output of the 17-bit x 17-bit
multiplier/scaler is a 33-bit value that is sign-extended
to 40 bits. Integer data is inherently represented as a
signed 2’s complement value, where the Most
Significant bit (MSb) is defined as a sign bit.
• The range of an N-bit 2’s complement integer is
• For a 16-bit integer, the data range is -32768
• For a 32-bit integer, the data range is
When the multiplier is configured for fractional
multiplication, the data is represented as a 2’s
complement fraction, where the MSb is defined as a
sign bit and the radix point is implied to lie just after the
sign bit (QX format). The range of an N-bit 2’s
complement fraction with this implied radix point is -1.0
to (1 – 2
is -1.0 (0x8000) to 0.999969482 (0x7FFF) including ‘0’
and has a precision of 3.01518x10
mode, the 16 x 16 multiply operation generates a 1.31
product that has a precision of 4.65661 x 10
The same multiplier is used to support the MCU
multiply instructions, which include integer 16-bit
signed, unsigned and mixed sign multiply operations.
The MUL instruction can be directed to use byte- or
word-sized operands. Byte operands will direct a 16-bit
result, and word operands will direct a 32-bit result to
the specified register(s) in the W array.
3.6.2
The
adder/subtracter with automatic sign extension logic. It
can select one of two accumulators (A or B) as its
pre-accumulation
destination. For the ADD and LAC instructions, the data
to be accumulated or loaded can be optionally scaled
using the barrel shifter prior to accumulation.
© 2009 Microchip Technology Inc.
-2
(0x8000) to 32767 (0x7FFF) including ‘0’.
-2,147,483,648 (0x8000 0000) to 2,147,483,647
(0x7FFF FFFF).
N-1
data
to 2
1-N
). For a 16-bit fraction, the Q15 data range
N-1
MULTIPLIER
DATA ACCUMULATORS AND
ADDER/SUBTRACTER
accumulator
– 1.
source
consists
and
post-accumulation
-5
. In Fractional
of
-10
a
.
40-bit
Preliminary
dsPIC33FJ12GP201/202
3.6.2.1
The adder/subtracter is a 40-bit adder with an optional
zero input into one side, and either true or complement
data into the other input.
• In the case of addition, the Carry/Borrow input is
• In the case of subtraction, the Carry/Borrow input
The adder/subtracter generates Overflow Status bits,
SA/SB and OA/OB, which are latched and reflected in
the STATUS register:
• Overflow from bit 39: this is a catastrophic
• Overflow into guard bits 32 through 39: this is a
The adder has an additional saturation block that
controls accumulator data saturation, if selected. It
uses the result of the adder, the Overflow Status bits
described
(CORCON<7:6>) and ACCSAT (CORCON<4>) mode
control bits to determine when, and to what value, to
saturate.
Six STATUS register bits have been provided to
support saturation and overflow:
• OA:
• OB:
• SA:
• SB:
• OAB: Logical OR of OA and OB
• SAB: Logical OR of SA and SB
The OA and OB bits are modified each time data
passes through the adder/subtracter. When set, they
indicate that the most recent operation has overflowed
into the accumulator guard bits (bits 32 through 39).
The OA and OB bits can also optionally generate an
arithmetic warning trap when OA and OB are set and
the corresponding Overflow Trap Flag Enable bits
(OVATE, OVBTE) in the INTCON1 register are set
(refer to Section 7.0 “Interrupt Controller”). This
allows the user application to take immediate action; for
example, to correct system gain.
active-high and the other input is true data (not
complemented).
is active-low and the other input is complemented.
overflow in which the sign of the accumulator is
destroyed.
recoverable overflow. This bit is set whenever all
the guard bits are not identical to each other.
or
or
ACCA overflowed into guard bits
ACCB overflowed into guard bits
ACCA saturated (bit 31 overflow and
saturation)
ACCA overflowed into guard bits and
saturated (bit 39 overflow and saturation)
ACCB saturated (bit 31 overflow and
saturation)
ACCB overflowed into guard bits and
saturated (bit 39 overflow and saturation)
Adder/Subtracter, Overflow and
Saturation
previously,
and
DS70264D-page 23
the
SAT<A:B>