PIC24FJ64GA002-I/SO Microchip Technology, PIC24FJ64GA002-I/SO Datasheet - Page 12

• Manufacturer Part Number: PIC24FJ64GA002-I/SO
• Description: IC PIC MCU FLASH 21KX24 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ64GA002-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 64KB (22K x 24)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C/IrDA/SPI/UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 5
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240011, DV164033, MA240013, AC164127, DM240002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10-ch x 10-bit
• Controller Family/series: PIC24
• No. Of I/o's: 21
• Ram Memory Size: 8KB
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Embedded Interface Type: I2C, SPI, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC162088 - HEADER MPLAB ICD2 24FJ64GA004 28AC164339 - MODULE SKT FOR PM3 28SOICDV164033 - KIT START EXPLORER 16 MPLAB ICD2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC24F Family Reference Manual
30.8
DS39714A-page 30-12
OPERATION IN POWER SAVE MODES
A word write is a simple process for a 16-bit polynomial. However, in some applications, byte
write operations may be used with 16-bit polynomials (e.g. in UART transmission/reception). In
these applications, an odd number of bytes may need to be padded up with an extra dummy byte.
A dummy byte should not be added if the message stream contains an even number of bytes. In
this case, the procedure explained above for 16-bit polynomials may need to be modified as
follows:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. For a partial result (CRC calculation is done but the FINAL_CALCULATION flag is not set),
30.7.5
For 10-bit or 12-bit polynomials, the CRC module calculates the checksums by taking into
account the 10 or 12 Least Significant bits of a word, respectively. For 10 bits of data, the Most
Significant 6 bits of a word may be programmed as zero. For 12-bit calculation, the Most
Significant 4 bits of a word may be programmed as zero. Refer to Section 30.5.2.1 “FIFO to
CRC Calculator” for more details.
After forming the words with 10 or 12 bits of actual data and the rest as don’t care bits, the same
steps as explained in Section 30.7.4 “16-Bit Polynomials” can be applied. For the
PLEN3:PLEN0 bits, use a value of 09h or 0Bh for 10-bit or 12-bit polynomials, respectively. A
suitable generator polynomial of the same length may be programmed in the CRCXOR register.
30.8.1
If Sleep mode is entered while the module is operating, the module is suspended in its current
state until clock execution resumes.
30.8.2
To continue full module operation in Idle mode, the CSIDL bit must be cleared prior to entry into
the mode.
If CSIDL = 1, the module behaves the same way as it does in Sleep mode; pending interrupt
events will be passed on, even though the module clocks are not available.
Program PLEN3:PLEN0 bits (CRCCON<3:0>) = 0Fh.
Program a value to CRCXOR (e.g., CRCXOR = 8005h).
Program a value in CRCWDAT:
• 0000h (for the start of a new calculation), or
• The previously calculated partial result (for part of the whole message stream).
If the CRCFUL bit is not set, and if all the data bytes of the message stream are not written
into the FIFO, then write a data byte to the CRCDAT register and increment a counter to
keep track of the number of bytes written to the FIFO.
If the CRCFUL bit is not set, and if all the data bytes of the message stream are already
written into the FIFO which are odd, then write a byte of 00h (dummy byte) to CRCDAT
and set a software flag in the software application (i.e., MESSAGE_OVER).
If the CRCFUL bit is not set and if all the data bytes of the message stream are already
written into the FIFO which are even, then set a software flag (MESSAGE_OVER).
If the CRCFUL bit is not set and if the MESSAGE_OVER flag is set, write a word of 0000h
to CRCDAT and set a software flag (i.e., FINAL_CALCULATION).
If the CRCFUL bit or the FINAL_CALCULATION flag is set, start CRC by setting the
CRCGO bit.
When CRCMPT is set, clear the CRCGO bit and read the result byte from the CRCWDAT
register.
pass the partial result to the next calculation process.
10-Bit or 12-Bit Polynomial
Sleep Mode
Idle Mode
Advance Information
© 2006 Microchip Technology Inc.