PIC24FJ64GA002-I/SO Microchip Technology, PIC24FJ64GA002-I/SO Datasheet - Page 8

• Manufacturer Part Number: PIC24FJ64GA002-I/SO
• Description: IC PIC MCU FLASH 21KX24 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ64GA002-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 64KB (22K x 24)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C/IrDA/SPI/UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 5
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240011, DV164033, MA240013, AC164127, DM240002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10-ch x 10-bit
• Controller Family/series: PIC24
• No. Of I/o's: 21
• Ram Memory Size: 8KB
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Embedded Interface Type: I2C, SPI, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC162088 - HEADER MPLAB ICD2 24FJ64GA004 28AC164339 - MODULE SKT FOR PM3 28SOICDV164033 - KIT START EXPLORER 16 MPLAB ICD2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC24F Family Reference Manual
30.5
DS39714A-page 30-8
CONTROL LOGIC
30.5.1
The FIFO is physically implemented as an 8-deep, 16-bit wide storage element. The logic
associated with the FIFO contains a 5-bit counter, called VWORD (VWORD4:VWORD0, or
CRCCON<12:8>). The value in the VWORD4:VWORD0 bits indicates the number of new data
elements in the FIFO.
The FIFO behaves as an 8-deep, 16-bit wide array when PLEN3:PLEN0 > 7, and a 16-deep,
8-bit wide array otherwise. The data for which the CRC is to be calculated must first be written
into the FIFO by the CPU using the CRCDAT register. Data must always be written into the
CRCDAT register. Reading of the CRCDAT register is not allowed and always returns zero.
The smallest data element that can be written into the FIFO is one byte. When
PLEN3:PLEN0
every word write operation.
If PLEN3:PLEN0 > 7, a word write into the FIFO increments the value of VWORD by one. A sin-
gle byte write to the CRCDAT register does not increment the value of VWORD; instead,
VWORD increments by one only after an even number of bytes (integer multiple of words) are
written into the CRCDAT register.
The CRCFUL bit is set (indicating the FIFO is full) when the value of VWORD reaches 8 (for the
8-deep, 16-bit FIFO configuration) or 16 (for the 16-deep, 8-bit FIFO configuration). The user
needs to ensure that the FIFO is not full while writing a new value to the CRCDAT register.
30.5.2
30.5.2.1
To start serial shifting from the FIFO to the CRC calculator, the CRCGO bit (CRCCON<4>) must
be set (= 1). The serial shifter starts shifting data, starting from the Most Significant bit first, into
the CRC engine only when CRCGO = 1 and the value of VWORD is greater than zero. If the
CRCFUL bit was set earlier, then it is cleared when VWORD decrements by one. VWORD dec-
rements by one when a FIFO location gets shifted completely to the CRC calculator. The serial
shifter continues shifting until VWORD reaches zero, at which point, the CRCMPT bit becomes
set to indicate that the FIFO is empty.
The frequency of the CRC shift clock is twice that of the PIC24F instruction clock cycle, thus
making this hardware shifting process faster than a software shifter. The users can write into the
FIFO while the shift operation is in progress. For a continuous data feed into the CRC engine,
the recommended mode of operation is to initially “prime” the FIFO with a sufficient number of
words or bytes. Once this is completely done, the user can start the CRC by setting the CRCGO
bit to
CRCFUL bit is not set, or the VWORD reads less than 8 or 16, another word can be written onto
the FIFO. At least one instruction cycle must pass after a write to the CRCDAT register before a
read of the VWORD bits is done.
To empty words already written into a FIFO, the CRCGO bit must be set to ‘1’ and the CRC shifter
must be allowed to run until the CRCMPT bit is set.
Note:
‘
1’. From this point onwards, either VWORD or the CRCFUL bit should be monitored. If the
FIFO
CRC Engine Interface
FIFO TO CRC CALCULATOR
When PLEN3:PLEN0 > 7, an integer multiple of words should be loaded into the
FIFO before the application software sets the CRCGO bit. If the CRCGO bit is set
after loading an odd number of bytes into the FIFO, the last odd byte is never shifted
out, and the CRCMPT bit always remains at ‘0’, indicating that the FIFO is not
empty.
≤
7, every byte write into the FIFO increments VWORD by one, or by two, for
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© 2006 Microchip Technology Inc.