PIC18F27J53-I/SP Microchip Technology, PIC18F27J53-I/SP Datasheet - Page 4

• Manufacturer Part Number: PIC18F27J53-I/SP
• Description: IC PIC MCU 128KB FLASH 28SPDIP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F27J53-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: *
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.8 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 8
• Operating Supply Voltage: 2.15 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Controller Family/series: PIC18
• Cpu Speed: 48MHz
• Embedded Interface Type: I2C, SPI, USART
• Digital Ic Case Style: DIP
• Supply Voltage Range: 1.8V To 5.5V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F47J53 FAMILY
4. Module: EUSART (Receive Baud Rate)
DS80506C-page 4
The EUSART may transmit and receive at
different baud rates under the following
circumstances:
• a system clock source other than the
• a CPU clock divider (CPDIV<1:0>,
This is because the receive baud rate clock
source is generated from a point prior to the
CPU prescaler, while the rest of the logic is
clocked at the system clock frequency (following
the prescaler).
Work around
Several work arounds are presented; others
may be available.
• If possible, use only a CPU divider of 1:1
• If the EUSART is being used to receive data
• Use two USART modules for communication:
Affected Silicon Revisions
A1
Secondary Oscillator has been selected, and
CONFIG1H<1:0>) other than 1:1 has been
programmed.
(CPDIV<1:0> = 11).
only, calculate the baud rate on the predivided
clock frequency. For example, if the system
clock frequency is 8 MHz and a CPU divider
setting of 2 is being used, use a clock
one to transmit data, and one to receive.
Calculate the baud rate for the receive
USART as described in the previous work
around. Calculate the transmit baud rate
normally using the actual (post-divider) clock
speed.
X
frequency of 16 MHz to calculate baud rate.
5. Module: Master Synchronous Serial Port
6. Module: Master Synchronous Serial Port
In Master I
occurs in the middle of an address or data
reception, the SCL clock stream will continue
endlessly and the RCEN bit of the SSPxCON2
register will remain set improperly. When a Start
condition occurs after the improper Stop condi-
tion, nine additional clocks will be generated
followed by the RCEN bit going low.
Work around
Use low-impedance pull-ups on the SDA line to
reduce the possibility of noise glitches that may
trigger an improper Stop event. Use a time-out
event timer to detect the unexpected Stop con-
dition, and subsequently, the stuck RCEN bit.
Clear the stuck RCEN bit by clearing the SSPEN
bit of SSPxCON1.
Affected Silicon Revisions
When configured for I
MSSP module may not receive the correct data, in
extremely rare cases. This occurs only if the Serial
Receive/Transmit Buffer register (SSPxBUF) is
not read after the SSP1IF interrupt (PIR1<3>) has
occurred, but before the first rising clock edge of
the next byte being received.
Work around
The issue can be resolved in either of these ways:
• Prior to the I
• Each time the SSPxIF is set, read the
A1
A1
X
clock stretching feature. This is done by setting
the SEN bit (SSPxCON2<0>).
SSPxBUF before the first rising clock edge of
the next byte being received.
X
2
(MSSP)
C Receive mode, if a Stop condition
2
C slave reception, enable the
 2010 Microchip Technology Inc.
2
C™ slave reception, the