DSPIC33FJ16GS404-I/ML Microchip Technology, DSPIC33FJ16GS404-I/ML Datasheet - Page 204
![IC DSPIC MCU/DSP 16K 44-QFN](/photos/6/81/68122/150-44-qfn_sml.jpg)
DSPIC33FJ16GS404-I/ML
Manufacturer Part Number
DSPIC33FJ16GS404-I/ML
Description
IC DSPIC MCU/DSP 16K 44-QFN
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ06GS101-ISO.pdf
(346 pages)
2.DSPIC33FJ06GS101-ISO.pdf
(18 pages)
3.DSPIC33FJ06GS101-ISO.pdf
(16 pages)
Specifications of DSPIC33FJ16GS404-I/ML
Program Memory Type
FLASH
Program Memory Size
16KB (16K x 8)
Package / Case
44-QFN
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
35
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
35
Data Ram Size
2 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- DSPIC33FJ06GS101-ISO PDF datasheet
- DSPIC33FJ06GS101-ISO PDF datasheet #2
- DSPIC33FJ06GS101-ISO PDF datasheet #3
- Current page: 204 of 346
- Download datasheet (6Mb)
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
REGISTER 15-4:
REGISTER 15-5:
DS70318D-page 202
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-3
bit 2-0
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-0
Note 1: The smallest pulse width that can be generated on the PWM output corresponds to a value of 0x0008,
R/W-0
R/W-0
R/W-0
R/W-0
2: As the duty cycle gets closer to 0% or 100% of the PWM period (0 ns-40 ns, depending on the mode of
while the maximum pulse width generated corresponds to a value of Period – 0x0008.
operation), the PWM duty cycle resolution will degrade from 1 LSB to 3 LSB.
SEVTCMP<15:3>: Special Event Compare Count Value bits
Unimplemented: Read as ‘0’
MDC<15:0>: Master PWM Duty Cycle Value bits
R/W-0
R/W-0
R/W-0
R/W-0
SEVTCMP: PWM SPECIAL EVENT COMPARE REGISTER
MDC: PWM MASTER DUTY CYCLE REGISTER
SEVTCMP <7:3>
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SEVTCMP <15:8>
Preliminary
MDC<15:8>
MDC<7:0>
U = Unimplemented bit, read as ‘0’
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
‘0’ = Bit is cleared
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
© 2009 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
R/W-0
R/W-0
R/W-0
U-0
—
R/W-0
R/W-0
R/W-0
U-0
—
bit 8
bit 0
bit 8
bit 0
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