PIC18F4420-I/P Microchip Technology, PIC18F4420-I/P Datasheet - Page 22

IC MCU FLASH 8KX16 40DIP

PIC18F4420-I/P

Manufacturer Part Number
PIC18F4420-I/P
Description
IC MCU FLASH 8KX16 40DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18F4420-I/P

Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
40-DIP (0.600", 15.24mm)
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
36
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
MSSP/SPI/I2C/PSP/USART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
36
Number Of Timers
4
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
13-ch x 10-bit
Package
40PDIP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DVA18XP400 - DEVICE ADAPTER 18F4220 PDIP 40LD444-1001 - DEMO BOARD FOR PICMICRO MCUACICE0206 - ADAPTER MPLABICE 40P 600 MIL
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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PIC18F2XXX/4XXX FAMILY
3.4
The ID locations are programmed much like the code
memory. The ID registers are mapped in addresses,
200000h through 200007h. These locations read out
normally even after code protection.
TABLE 3-8:
DS39622L-page 22
Step 1: Direct access to code memory and enable writes.
Step 2: Load write buffer with 8 bytes and write.
Note:
Command
0000
0000
0000
0000
0000
0000
0000
0000
1101
1101
1101
1111
0000
4-Bit
ID Location Programming
The user only needs to fill the first 8 bytes
of the write buffer in order to write the ID
locations.
8E A6
9C A6
0E 20
6E F8
0E 00
6E F7
0E 00
6E F6
<MSB><LSB>
<MSB><LSB>
<MSB><LSB>
<MSB><LSB>
00 00
WRITE ID SEQUENCE
Data Payload
BSF
BCF
MOVLW 20h
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 00h
MOVWF TBLPTRL
Write 2 bytes and post-increment address by 2.
Write 2 bytes and post-increment address by 2.
Write 2 bytes and post-increment address by 2.
Write 2 bytes and start programming.
NOP - hold PGC high for time P9 and low for time P10.
EECON1, EEPGD
EECON1, CFGS
Table 3-8
write the ID locations.
In order to modify the ID locations, refer to the method-
ology described in
Memory”. As with code memory, the ID locations must
be erased before being modified.
Core Instruction
demonstrates the code sequence required to
Section 3.2.1 “Modifying Code
 2010 Microchip Technology Inc.

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