PIC18F2331-I/SO Microchip Technology, PIC18F2331-I/SO Datasheet - Page 64
![IC PIC MCU FLASH 4KX16 28SOIC](/photos/6/59/65909/150-28-soic_sml.jpg)
PIC18F2331-I/SO
Manufacturer Part Number
PIC18F2331-I/SO
Description
IC PIC MCU FLASH 4KX16 28SOIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC18F2331-ISO.pdf
(392 pages)
4.PIC18F2331-ISO.pdf
(8 pages)
5.PIC18F2331-ISO.pdf
(6 pages)
6.PIC18F2331-ISO.pdf
(16 pages)
7.PIC18F4331-EP.pdf
(400 pages)
Specifications of PIC18F2331-I/SO
Core Size
8-Bit
Program Memory Size
8KB (4K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
Number Of I /o
24
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Controller Family/series
PIC18
No. Of I/o's
24
Eeprom Memory Size
256Byte
Ram Memory Size
768Byte
Cpu Speed
40MHz
No. Of Timers
4
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
EUSART, I2C, SPI, SSP
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
24
Number Of Timers
1 x 8
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, ICE2000, DM183021, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Package
28SOIC W
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MILI3-DB18F4431 - BOARD DAUGHTER ICEPIC3
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F2331-I/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC16F818-ISO PDF datasheet #2
- PIC18F2331-ISO PDF datasheet #3
- PIC18F2331-ISO PDF datasheet #4
- PIC18F2331-ISO PDF datasheet #5
- PIC18F2331-ISO PDF datasheet #6
- PIC18F4331-EP PDF datasheet #7
- Current page: 64 of 392
- Download datasheet (4Mb)
PIC18F2331/2431/4331/4431
6.1.2.3
Since the Top-of-Stack (TOS) is readable and writable,
the ability to push values onto the stack and pull values
off the stack without disturbing normal program execu-
tion is a desirable option. To push the current PC value
onto the stack, a PUSH instruction can be executed.
This will increment the Stack Pointer and load the
current PC value onto the stack. TOSU, TOSH and
TOSL can then be modified to place data or a return
address on the stack.
The PUSH instruction places the current PC value onto
the stack. This increments the Stack Pointer and loads
the current PC value onto the stack. The POP instruc-
tion discards the current TOS by decrementing the
Stack Pointer. The previous value pushed onto the
stack then becomes the TOS value.
6.1.2.4
These Resets are enabled by programming the
STVREN bit in Configuration Register 4L. When the
STVREN bit is cleared, a full or underflow condition will
set the appropriate STKFUL or STKUNF bit, but not
cause a device Reset. When the STVREN bit is set, a
full or underflow condition will set the appropriate
STKFUL or STKUNF bit and then cause a device
Reset. The STKFUL or STKUNF bits are cleared by the
user software or a Power-on Reset.
6.1.3
A Fast Register Stack is provided for the STATUS,
WREG and BSR registers, to provide a “fast return”
option for interrupts. The stack for each register is only
one level deep and is neither readable nor writable. It is
loaded with the current value of the corresponding
register when the processor vectors for an interrupt. All
interrupt sources will push values into the stack
registers.
The values in the registers are then loaded back into
their associated registers if the RETFIE, FAST instruc-
tion is used to return from the interrupt. If both low and
high-priority interrupts are enabled, the stack registers
cannot be used reliably to return from low-priority inter-
rupts. If a high-priority interrupt occurs while servicing a
low-priority interrupt, the stack register values stored by
the low-priority interrupt will be overwritten. In these
cases, users must save the key registers in software
during a low-priority interrupt.
If interrupt priority is not used, all interrupts may use the
Fast Register Stack for returns from interrupt. If no
interrupts are used, the Fast Register Stack can be
used to restore the STATUS, WREG and BSR registers
at the end of a subroutine call. To use the Fast Register
Stack for a subroutine call, a CALL label, FAST
instruction must be executed to save the STATUS,
WREG and BSR registers to the Fast Register Stack. A
RETURN, FAST instruction is then executed to restore
these registers from the Fast Register Stack.
DS39616D-page 64
FAST REGISTER STACK
PUSH and POP Instructions
Stack Full/Underflow Resets
Example 6-1
the Fast Register Stack during a subroutine call and
return.
EXAMPLE 6-1:
6.1.4
There may be programming situations that require the
creation of data structures, or look-up tables, in
program memory. For PIC18 devices, look-up tables
can be implemented two ways:
• Computed GOTO
• Table Reads
6.1.4.1
A computed GOTO is accomplished by adding an offset
to the program counter. An example is shown in
Example
A look-up table can be formed with an ADDWF PCL
instruction and a group of RETLW nn instructions. The
W register is loaded with an offset into the table before
executing a call to that table. The first instruction of the
called routine is the ADDWF PCL instruction. The next
instruction executed will be one of the RETLW nn
instructions that returns the value “nn” to the calling
function.
The offset value (in WREG) specifies the number of
bytes that the program counter should advance and
should be multiples of 2 (LSb = 0).
In this method, only one data byte can be stored in
each instruction location and room on the return
address stack is required.
EXAMPLE 6-2:
CALL SUB1, FAST
SUB1
ORG
TABLE
RETURN FAST
6-2.
.
.
.
MOVFW
CALL
0xnn00
ADDWF
RETLW
RETLW
RETLW
LOOK-UP TABLES IN PROGRAM
MEMORY
shows a source code example that uses
Computed GOTO
FAST REGISTER STACK
CODE EXAMPLE
COMPUTED GOTO USING
AN OFFSET VALUE
;STATUS, WREG, BSR
;SAVED IN FAST REGISTER
;STACK
;IN FAST REGISTER STACK
2010 Microchip Technology Inc.
;RESTORE VALUES SAVED
OFFSET
TABLE
PCL
0xnn
0xnn
0xnn
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