PIC16F84A-20I/P Microchip Technology, PIC16F84A-20I/P Datasheet - Page 353

• Manufacturer Part Number: PIC16F84A-20I/P
• Description: IC MCU FLASH 1KX14 EE 18DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F84A-20I/P

• Program Memory Type: FLASH
• Program Memory Size: 1.75KB (1K x 14)
• Package / Case: 18-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: POR, WDT
• Number Of I /o: 13
• Eeprom Size: 64 x 8
• Ram Size: 68 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 68 B
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 1
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: - 40 C
• Data Rom Size: 64 B
• Height: 3.3 mm
• Length: 22.86 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4 V
• Width: 6.35 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3-DB16F84A - BOARD DAUGHTER ICEPIC3DVA16XP180 - ADAPTER DEVICE FOR MPLAB-ICEAC164010 - MODULE SKT PROMATEII DIP/SOIC
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

18.5.2
PIR
RCSTA
RCREG
PIE
TXSTA
SPBRG Baud Rate Generator Register
Legend: x = unknown, - = unimplemented read as '0'.
Note 1: The position of this bit is device dependent.
Name
1997 Microchip Technology Inc.
Shaded cells are not used for Synchronous Master Reception.
USART Synchronous Master Reception
SPEN
CSRC
Bit 7
RX7
Once Synchronous mode is selected, reception is enabled by setting either of the SREN
(RCSTA<5>) or CREN (RCSTA<4>) bits. Data is sampled on the RX/DT pin on the falling edge
of the clock. If the SREN bit is set, then only a single word is received. If the CREN bit is set, the
reception is continuous until the CREN bit is cleared. If both bits are set then the CREN bit takes
precedence. After clocking the last serial data bit, the received data in the Receive Shift Register
(RSR) is transferred to the RCREG register (if it is empty). When the transfer is complete, the
RCIF interrupt flag bit is set. The actual interrupt can be enabled/disabled by setting/clearing the
RCIE enable bit. The RCIF flag bit is a read only bit which is cleared by the hardware. In this case
it is cleared when the RCREG register has been read and is empty. The RCREG is a double buff-
ered register, i.e. it is a two deep FIFO. It is possible for two bytes of data to be received and
transferred to the RCREG FIFO and a third byte to begin shifting into the RSR register. On the
clocking of the last bit of the third byte, if the RCREG register is still full then overrun error bit,
OERR (RCSTA<1>), is set and the word in the RSR is lost. The RCREG register can be read
twice to retrieve the two bytes in the FIFO. The OERR bit has to be cleared in software (by clear-
ing the CREN bit). If the OERR bit is set, transfers from the RSR to the RCREG are inhibited, so
it is essential to clear the OERR bit if it is set. The 9th receive bit is buffered the same way as the
receive data. Reading the RCREG register will load the RX9D bit with a new value, therefore it
is essential for the user to read the RCSTA register before reading RCREG in order not to lose
the old (previous) information in the RX9D bit.
Steps to follow when setting up a Synchronous Master Reception:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. If any error occurred, clear the error by clearing the CREN bit.
Table 18-9: Registers Associated with Synchronous Master Reception
Bit 6
RX9
RX6
TX9
Initialize the SPBRG register for the appropriate baud rate. (Subsection
Baud Rate Generator (BRG)”
Enable the synchronous master serial port by setting the SYNC, SPEN, and CSRC bits.
Ensure that the CREN and SREN bits are clear.
If interrupts are desired, then set the RCIE bit.
If 9-bit reception is desired, then set the RX9 bit.
If a single reception is required, set the SREN bit. For continuous reception set the CREN
bit.
The RCIF bit will be set when reception is complete and an interrupt will be generated if
the RCIE bit was set.
Read the RCSTA register to get the ninth bit (if enabled) and determine if any error
occurred during reception.
Read the 8-bit received data by reading the RCREG register.
SREN CREN
TXEN SYNC
Bit 5
RX5
Bit 4
RX4
RCIE
RCIF
Bit 3
RX3
—
—
(1)
(1)
BRGH
FERR
Bit 2
)
RX2
Section 18. USART
OERR
TRMT
Bit 1
RX1
RX9D
TX9D
Bit 0
RX0
0000 -00x
0000 0000
0000 -010
0000 0000
Value on:
POR,
BOR
0
0
DS31018A-page 18-17
18.3 “USART
other Resets
Value on all
0000 -00x
0000 0000
0000 -010
0000 0000
0
0
18